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6048C–ATARM–29-Jun-06
AT91SAM7A1
5. Architectural Overview
The AT91SAM7A1 architecture consists of two main buses, the Advanced System Bus (ASB)
and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It
interfaces the processor with the on-chip 32-bit memories and the external memories and
devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-
chip peripherals and is optimized for low power consumption. The AMBA
™
Bridge provides an
interface between the ASB and the APB.
The AT91SAM7A1 peripherals are designed to be programmed with a minimum number of
instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 1 Mbytes of
the 4 Gbyte address space. Except for the interrupt controller, the peripheral base address is the
lowest address of its memory space. The peripheral register set is composed of control, mode,
data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently-
written registers are mapped into three memory locations. The first address is used to set the
individual register bits, the second resets the bits and the third address reads the value stored in
the register. A bit can be set or reset by writing a one to the corresponding position at the appro-
priate address. Writing a zero has no effect. Individual bits can thus be modified without having
to use costly read-modify-write and complex bit manipulation instructions.
The ARM7TDMI processor operates in little-endian mode in the AT91SAM7A1 microcontroller.
The processor's internal architecture and the ARM and Thumb instruction sets are described in
the ARM7TDMI datasheet. The ARM Standard In-Circuit-Emulation debug interface is sup-
ported via the ICE port of the AT91SAM7A1 microcontroller (This is not a standard IEEE 1149.1
JTAG Boundary Scan interface).
6. Advanced Memory Controller (AMC)
The AT91SAM7A1 embeds 4 Kbytes of internal SRAM. The internal memory is directly con-
nected to the 32-bit data bus and is single-cycle accessible. This provides maximum
performance of 36 MIPS @ 40 MHz by using the ARM instruction set of the processor, minimiz-
ing system power consumption and improving on the performance of separate memory
solutions.
7. External Bus Interface (EBI)
The EBI generates the signals that control the accesses to the external memories or peripheral
devices. The EBI is fully programmable and can address up to 6 Mbytes. It has four chip selects
and a 21-bit address bus, the upper bit of which is multiplexed with a chip select. Separate read
and write control signals allow for direct memory and peripheral interfacing. The EBI supports
different access protocols, allowing single clock cycle memory accesses. The main features are:
• External Memory Mapping
• Up to 4 chip select lines
• Byte write or byte select lines
• 8-bit or 16-bit data bus
• External wait
• Remap of boot memory
• Two different read protocols
• Programmable wait state generation
