JPEG2000 Video Codec
Data Sheet
ADV202
Rev. D
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FEATURES
Complete single-chip JPEG2000 compression and
decompression solution for video and still images
Patented SURF® (spatial ultra-efficient recursive filtering)
technology enables low power and low cost wavelet-
based compression
Supports both 9/7 and 5/3 wavelet transforms with up to
6 levels of transform
Programmable tile/image size with widths up to 2048 pixels in
3-component 4:2:2 interleaved mode, and up to 4096 pixels
in single-component mode
Maximum tile/image width: 4096 pixels
Video interface directly supporting ITU.R-BT656,
SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M (525p),
ITU.R-BT1358 (625p) or any video format with a maximum
input rate of 65 MSPS for irreversible mode or 40 MSPS for
reversible mode
Two or more ADV202s can be combined to support full-
frame SMPTE274M HDTV (1080i) or SMPTE296M (720p)
Flexible asynchronous SRAM-style host interface allows
glueless connection to most 16-/32-bit microcontrollers
and ASICs
2.5 V to 3.3 V I/O and 1.5 V core supply
12 mm × 12 mm 121-lead CSPBGA, speed grade 115 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 135 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 150 MHz
APPLICATIONS
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders
GENERAL DESCRIPTION
The ADV202 is a single-chip JPEG2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and feature set provided
by the JPEG2000 (J2K)ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG2000 image compression standard as well
as providing fully compliant code-stream generation for most
applications.
The ADV202’s dedicated video port provides glueless connection
to common digital video standards such as ITU.R-BT656,
SMPTE125M, SMPTE293M (525p), ITU.R-BT1358 (625p),
SMPTE274M (1080i), or SMPTE296M (720p). A variety of other
high speed, synchronous pixel and video formats can also be sup-
ported using the programmable framing and validation signals.
(continued on Page 4)
FUNCTIONAL BLOCK DIAGRAM
PIXEL I/F
EXTERNAL
DMA CTRL
PIXEL FIFO
CODE FIFO
ATTR FIFO
WAVELET
ENGINE
INTERNAL BUS AND DMA ENGINE
EMBEDDED
RISC
PROCESSOR
SYSTEM
PIXEL I/F
HOST I/F
EC1 EC2
RAM ROM
EC3
04723-001
ADV202
Figure 1.
ADV202* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Application Notes
AN-790: How to Use the ADV202
AN-796: Using the ADV202 in a Multichip Application
AN-799: ADV202 Test Modes
Data Sheet
ADV202: JPEG2000 Video Codec Data Sheet
REFERENCE MATERIALS
Technical Articles
ADV202 Technical Documentation
Digital 3-D at a Theater Near You
HDTV Over UWB: Wireless Video Streaming Trials and
Quality of Service Analysis
Implementing JPEG2000 compression
IP Centric Calls for Scalable Compression
JPEG2000 Codec for Robust, Scalable Pro and Consumer
Video
DESIGN RESOURCES
ADV202 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all ADV202 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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ADV202 Data Sheet
Rev. D | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
JPEG2000 Feature Support.......................................................... 4
Specifications ..................................................................................... 5
Supply Voltages and Current ...................................................... 5
Input/Output Specifications ........................................................ 5
Clock and
RESET
Specifications ................................................ 6
Normal Host ModeRead Operation ...................................... 7
Normal Host ModeWrite Operation ..................................... 8
DREQ
/
DACK
DMA ModeSingle FIFO Write Operation .. 9
DREQ
/
DACK
DMA ModeSingle FIFO Read Operation . 11
External DMA ModeFIFO Write, Burst Mode .................. 13
External DMA ModeFIFO Read, Burst Mode ................... 14
Streaming Mode (JDATA)FIFO Read/Write ...................... 16
VDATA Mode Timing ............................................................... 17
Raw Pixel Mode Timing ............................................................ 18
Absolute Maximum Ratings .......................................................... 19
Thermal Resistance .................................................................... 19
ESD Caution ................................................................................ 19
Pin BGA Assignments and Function Descriptions ................... 20
Pin BGA Assignments ............................................................... 20
Pin Function Descriptions ........................................................ 23
Theory of Operation ...................................................................... 26
Wavelet Engine ........................................................................... 26
Entropy Codecs........................................................................... 26
Embedded Processor System .................................................... 26
Memory System .......................................................................... 26
Internal DMA Engine ................................................................ 26
ADV202 Interface........................................................................... 27
Video Interface (VDATA Bus) .................................................. 27
Host Interface (HDATA Bus) ................................................... 27
Direct and Indirect Registers .................................................... 27
Control Access Registers ........................................................... 27
Pin Configuration and Bus Sizes/Modes ................................ 28
Stage Register .............................................................................. 28
JDATA Mode............................................................................... 28
External DMA Engine ............................................................... 28
Internal Registers ............................................................................ 29
Direct Registers ........................................................................... 29
Indirect Registers ........................................................................ 30
PLL ............................................................................................... 31
Hardware Boot ............................................................................ 31
Video Input Formats ...................................................................... 32
Applications ..................................................................................... 34
EncodeMultichip Mode ......................................................... 34
DecodeMultichip Master/Slave ............................................ 35
Digital Still Camera/Camcorder .............................................. 35
Encode/Decode SDTV Video Application ............................. 36
ASIC Application (32-Bit Host/32-Bit ASIC) ......................... 37
HIPI (Host InterfacePixel Interface) ................................... 38
JDATA Interface ......................................................................... 38
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 40

ADV202BBCZRL-150

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 Video IC 150 MHz
Lifecycle:
New from this manufacturer.
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