OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADV202BBCZRL-150

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
ADV202 Data Sheet
Rev. D | Page 24 of 40
Mnemonic
Pins
Used 121-Lead Package 144-Lead Package I/O Description
HOLD
I External Hold Indication for JDATA Input/Output Stream.
Polarity is programmable in the EDMOD0 register. This pin
is always an input.
FCS0
I Used in DCS-DMA Mode. Chip select for the FIFO assigned
to Channel 0 (asynchronous mode).
DREQ1
1 F10 F10 O Data Request for External DMA Interface. Indicates that
the ADV202 is ready to send/receive data to/from the FIFO
assigned to DMA Channel 1.
FSRQ1
O Used in DCS-DMA Mode. Service request from the FIFO
assigned to Channel 1 (asynchronous mode).
CFG[2] I Boot Mode Configuration. This pin is read on reset to
determine the boot configuration of the on-board
processor. The pin should be tied to IOVDD or DGND
through a 10 kΩ resistor.
DACK1
1 G9 F9 I Data Acknowledge for External DMA Interface. Signal
from the host CPU, which indicates that the data transfer
request (
DREQ1
) has been acknowledged and data
transfer can proceed. This pin must be held high at all
times unless a DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA interface is not
used, even if the DMA channels are disabled.
FCS1
I Used in DCS-DMA Mode. Chip select for the FIFO assigned
to Channel 1 (asynchronous mode).
HDATA[31:28] 4 J2 to J4, H1 K3, J1 to J3 I/O Host Expansion Bus.
JDATA[7:4] I/O JDATA Bus (JDATA Mode).
HDATA[27:24] 4 H2 to H4, G4 J4, H1 to H3 I/O Host Expansion Bus.
JDATA[3:0] I/O JDATA Bus (JDATA Mode).
HDATA[23:16] 8 G3, G2, F4, F3, F2 E2,
E3, E4
H4, G1 to G4, F1 to F3 I/O Host Expansion Bus.
SCOMM[7] 8 L2 M2 I/O When not used, this pin should be tied low via a 10 kΩ
resistor.
SCOMM[6] L3 M3 I/O When not used, this pin should be tied low via a 10 kΩ
resistor.
SCOMM[5] L4 M4 I/O This pin must be used in multiple chip mode to align the
outputs of two or more ADV202s. For details, see the
Applications section and AN-796 ADV202 Multichip
Application application note. When not used, this pin
should be tied low via a 10 kΩ resistor.
SCOMM[4] K1 L1 O LCODE Output in Encode Mode. When LCODE is enabled,
the output on this pin indicates on a high transition that
the last data-word for a field has been read from the FIFO.
For an 8-bit interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled by default.
SCOMM[3] K2 L2 O This pin should be tied low via a 10 kΩ resistor.
SCOMM[2] L5 L3 O This pin should be tied low via a 10 kΩ resistor.
SCOMM[1] K4 K1 I This pin should be tied low via a 10 kΩ resistor.
SCOMM[0] K3 K2 O This pin should be tied low via a 10 kΩ resistor.
VCLK 1 E9 E12 I Video Data Clock. Must be supplied if video data is
input/output on the VDATA bus.
VDATA[11:0] 12 D11, D10, C7, C9,
C10, B7, B8, B9, B11,
B10, A7, A10
D10 to D12,
C10 to C12,
B10 to B12, A9 to A11
I/O Video Data. Unused pins should be pulled down via a
10 kΩ resistor.
VSYNC 1 D8 E10 I/O Vertical Sync for Video Mode.
VFRM Raw Pixel Mode Framing Signal. Indicates first sample of a
tile when asserted high.
HSYNC 1 D9 E11 I/O Horizontal Sync for Video Mode.
VRDY O Raw Pixel Mode Ready Signal.
Data Sheet ADV202
Rev. D | Page 25 of 40
Mnemonic
Pins
Used 121-Lead Package 144-Lead Package I/O Description
FIELD 1 E10 E9 I/O Field Sync for Video Mode.
VSTRB I Raw Pixel Mode Transfer Strobe.
TEST1 1 J6 K12 I This pin should be connected to ground via a pull-down
resistor.
TEST2 1 K9 K11 I This pin should be connected to ground via a pull-down
resistor.
TEST3 1 J10 K10 I This pin should be connected to ground via a pull-down
resistor.
TEST4 1 L6 M9 I This pin should be connected to ground via a pull-down
resistor.
TEST5 1 K10 L10 O No Connect.
VDD A3, A8, D7, H7 B6, B7, C6, C7, D6, D7,
J6, J7, K6, K7, L6, L7
V Positive Supply for Core.
DGND A1, A11, A4, A9, C1,
C11, D6, E1, E5 to E7,
E11, F1, F5 to F7,
F11, G1, G5 to G7,
G11, H6, J1, J11,
K11, L1, L8, L11
A1, A5 to A8, A12, B5,
B8, C5, C8, D5, D8, E4
to E8, F5 to F8, G5 to
G9, H5 to H9, J5, J8 to
J9, K5, K8, L5, L8, M1,
M5 to M8, M11, M12
GND Ground.
PLLVDD 1 L10 M10 V Positive Supply for PLL.
IOVDD B6, C6, C8, D5, E8,
G8, H5, J5, K5, K6, K7
B4, B9, C4, C9, D4, D9,
K4, K9, L4, L9
V Positive Supply for I/O.
ADV202 Data Sheet
Rev. D | Page 26 of 40
THEORY OF OPERATION
The input video or pixel data is passed on to the ADV202’s pixel
interface, where samples are de-interleaved and passed on to the
wavelet engine, which decomposes each tile or frame into
subbands using the 5/3 or 9/7 filters. The resulting wavelet
coefficients are then written to internal memory. Next, the
entropy codecs code the image data so it conforms to the
JPEG2000 standard. An internal DMA provides high
bandwidth memory-to-memory transfers, as well as high
performance transfers between functional blocks and memory.
WAVELET ENGINE
The ADV202 provides a dedicated wavelet transform processor
based on Analog Devices’ proven and patented SURF
technology. This processor can perform up to six wavelet
decomposition levels on a tile. In encode mode, the wavelet
transform processor takes in uncompressed samples, performs
the wavelet transform and quantization, and writes the wavelet
coefficients in all frequency subbands to internal memory. Each
of these subbands is then further broken down into code blocks.
The code-block dimensions can be user-defined and are used
by the wavelet transform processor to organize the wavelet
coefficients into code blocks when writing to internal memory.
Each completed code block is then entropy coded by one of the
entropy codecs.
In decode mode, wavelet coefficients are read from internal
memory and recomposed into uncompressed samples.
ENTROPY CODECS
The entropy codec block performs context modeling and
arithmetic coding on a code block of the wavelet coefficients.
Additionally, this block performs the distortion metric
calculations during compression that are required for optimal
rate and distortion performance. Because the entropy coding
process is the most computationally intensive operation in the
JPEG2000 compression process, three dedicated hardware
entropy codecs are provided on the ADV202.
EMBEDDED PROCESSOR SYSTEM
The ADV202 incorporates an embedded 32-bit RISC processor.
This processor is used for configuration, control, and manage-
ment of the dedicated hardware functions, as well as for parsing
and generating the JPEG2000 code stream. The processor
system includes memory for both program and data memory,
an interrupt controller, standard bus interfaces, and other
hardware functions such as timers and counters.
MEMORY SYSTEM
The memory system’s main function is to manage wavelet
coefficient data, interim code-block attribute data, and
temporary work space for creating, parsing, and storing the
JPEG2000 code stream. The memory system can also be used
for program and data memory for the embedded processor.
INTERNAL DMA ENGINE
The internal DMA engine provides high bandwidth memory-
to-memory transfers, as well as high performance transfers
between memory and functional blocks. This function is critical
for high speed generation and parsing the code stream.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

ADV202BBCZRL-150

Mfr. #:
Buy ADV202BBCZRL-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 Video IC 150 MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet