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ADV202BBCZRL-150

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
ADV202 Data Sheet
Rev. D | Page 36 of 40
ENCODE/DECODE SDTV VIDEO APPLICATION
Figure 27 shows two ADV202 chips using 10-bit CCIR656 in normal host mode.
04723-005
ENCODE MODE
32-BIT
HOST CPU
ADV202
HDATA[31:0]DATA[31:0]
10-BIT
VIDEO
DECODER
IRQINTR
ADDR[3:0]ADDR[3:0]
P[19:10]VDATA[11:2]
VIDEO IN
LLC1
VCLK
MCLK
CSCS
RDRD
WEWE
ACKACK
27MHz
OSC
DECODE MODE
32-BIT
HOST CPU
ADV202
HDATA[31:0]DATA[31:0]
10-BIT
VIDEO
ENCODER
IRQINTR
ADDR[3:0]ADDR[3:0]
P[9:0]VDATA[11:2]
VIDEO OUT
CLKINVCLK
MCLK
CSCS
RDRD
WEWE
ACKACK
Figure 27. Encode/Decode—SDTV Video Application
Data Sheet ADV202
Rev. D | Page 37 of 40
ASIC APPLICATION (32-BIT HOST/32-BIT ASIC)
Figure 28 shows two ADV202 chips using 10-bit CCIR656 in normal host mode.
04723-006
ENCODE MODE
32-BIT
HOST CPU
ADV202
DATA[31:0]
IRQIRQ
ADDR[3:0]ADDR[3:0]
CSCS
RD
RD
WEWE
ACKACK
ASIC
10-BIT
VIDEO
DECODER
P[19:10]
LLC1
VDATA[11:2]
VIDEO IN
VCLK
MCLK
DREQ0DREQ0
DACK0DACK0
HDATA[31:0]DATA[31:0]
27MHz
OSC
DECODE MODE
31 -BIT
HOST CPU
ADV202
DATA[31:0]
IRQIRQ
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK
ASIC
10-BIT
VIDEO
ENCODER
P[9:0]VDATA[11:2]
VIDEO OUT
CLKINVCLK
MCLK
DREQ0DREQ0
DACK0DACK0
HDATA[31:0]DATA[31:0]
Figure 28. Encode/Decode ASIC Application
ADV202 Data Sheet
Rev. D | Page 38 of 40
HIPI (HOST INTERFACE—PIXEL INTERFACE)
Figure 29 is a typical configuration using HIPI mode.
04723-007
HDATA<31>Y0/G0<MSB>
HDATA<30>
Y0/G0<6>
HDATA<29>Y0/G0<5>
HDATA<28>Y0/G0<4>
HDATA<27>Y0/G0<3>
HDATA<26>Y0/G0<2>
HDATA<25>Y0/G0<1>
HDATA<24>Y0/G0<0>
HDATA<23>Cb0/G1<MSB>
HDATA<22>Cb0/G1<6>
HDATA<21>Cb0/G1<5>
HDATA<20>Cb0/G1<4>
HDATA<19>Cb0/G1<3>
HDATA<18>Cb0/G1<2>
HDATA<17>Cb0/G1<1>
HDATA<16>Cb0/G1<0>
HDATA<15>Y1/G2<MSB>
HDATA<14>Y1/G2<6>
HDATA<13>
Y1/G2<5>
HDATA<12>Y1/G2<4>
HDATA<11>Y1/G2<3>
HDATA<10>Y1/G2<2>
HDATA<9>Y1/G2<1>
HDATA<8>Y1/G2<0>
HDATA<7>Cr0/G3<MSB>
HDATA<6>Cr0/G3<6>
HDATA<5>Cr0/G3<5>
HDATA<4>Cr0/G3<4>
HDATA<3>Cr0/G3<3>
HDATA<2>Cr0/G3<2>
HDATA<1>Cr0/G3<1>
HDATA<0>Cr0/G3<0>
CS
DATA [31:0]
CS
RD RD
WR
WE
ACK
ACK
IRQ
IRQ
DREQ DREQ0
DACK DACK0
MCLK
74.25MHz
DREQ DREQ1
DACK
DACK1
32-BIT HOST
RAW PIXEL
DATAPATH
COMPRESSED
DATAPATH
Figure 29. Host Interface—Pixel Interface Mode
JDATA INTERFACE
Figure 30 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR656.
04723-008
16-BIT
HOST CPU
ASIC
ADV202
HDATA[15:0]DATA[15:0]
IRQIRQ
ADDR[3:0]ADDR[3:0]
P[19:10]VDATA[11:2]
FIELDFIELD
VSVSYNC
HS
LLC1
HSYNC
VCLK
MCLK
VIDEO IN
YCrCb
CSCS
JDATA[7:0]
HOLD
VALID
RDRD
WE
WE
ACKACK
Figure 30. JDATA Application
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

ADV202BBCZRL-150

Mfr. #:
Buy ADV202BBCZRL-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 Video IC 150 MHz
Lifecycle:
New from this manufacturer.
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