SSC7150-ML-AB0 Datasheet SSC7150-ML-AB0, SSC7150-ML-AB0-TR | P13-P15

 2015 Microchip Technology Inc. DS00001885A-page 13

SSC7150

3.4 Master Clear (MCLR#) Pin

The MCLR# pin is the Device Reset pin. Pulling the MCLR# pin low generates a device Reset. Figure 3-2 illustrates a

typical MCLR# circuit.

FIGURE 3-2: MCLR# PIN CONNECTIONS

Note 1: 470Ω≤R1 ≤ 1Ω will limit any current flowing into

MCLR# from the external capacitor C, in the event of

MCLR# pin breakdown, due to Electrostatic Dis-

charge (ESD) or Electrical Overstress (EOS).

2: The capacitor can be sized to prevent unintentional

Resets from brief glitches or to extend the device

Reset period during POR.

(1)

10k

MCLR#

SSC7150

1 kΩ

0.1 µF

(2)

PGECx

(3)

PGEDx

(3)

ICSP™

VSS

Recommended Components:

SSC7150

DS00001885A-page 14  2015 Microchip Technology Inc.

4.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the SSC7150 electrical characteristics. Additional information will be provided in

future revisions of this document as it becomes available.

Absolute maximum ratings for the SSC7150 devices are listed below. Exposure to these maximum rating conditions for

extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above

the parameters indicated in the operation listings of this specification, is not implied.

Absolute Maximum Ratings

(See Note 1)

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on V

DD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any pin that is not 5V tolerant, with respect to V

SS (Note 3) ....................................... - 0.3V to (VDD + 0.3V)

Voltage on any 5V tolerant pin with respect to V

SS when VDD ≥ 2.3V (Note 3) ....................................... - 0.3V to +5.5V

Voltage on any 5V tolerant pin with respect to V

SS when VDD < 2.3V (Note 3)....................................... - 0.3V to +3.6V

Maximum current out of V

SS pin(s) .......................................................................................................................300 mA

Maximum current into V

DD pin(s) (Note 2)........................................................................................................... 300 mA

Maximum output current sunk by any I/O pin..........................................................................................................15 mA

Maximum output current sourced by any I/O pin.....................................................................................................15 mA

Maximum current sunk by all ports........................................................................................................................200 mA

Maximum current sourced by all ports (Note 2) ....................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions,

above those indicated in the operation listings of this specification, is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 4-1).

3: See the “Pin List” section for the 5V tolerant pins.

 2015 Microchip Technology Inc. DS00001885A-page 15

SSC7150

4.1 DC Characteristics

TABLE 4-1: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typical Max. Unit

Industrial Temperature Devices

Operating Junction Temperature Range TJ -40 — +125 °C

Operating Ambient Temperature Range T

A -40 — +85 °C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD – S IOH)

D PINT + PI/O W

I/O Pin Power Dissipation:

I/O = S (({V

DD – VOH} x IOH) + S (VOL x IOL))

Maximum Allowed Power Dissipation P

DMAX (TJ – TA)/θJA W

TABLE 4-2: THERMAL PACKAGING CHARACTERISTICS

Characteristics Symbol Typical Max. Unit Notes

Package Thermal Resistance, 28-pin QFN θ

JA 35 — °C/W 1

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

TABLE 4-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C

Param.

No.

Symbol Characteristics Min. Typ. Max. Units Conditions

Operating Voltage

DC10 V

DD Supply Voltage (Note 2) 2.3 — 3.6 V —

DC12 V

DR RAM Data Retention Voltage

(Note 1)

1.75 — — V —

DC16 VPOR VDD Start Voltage

to Ensure Internal Power-on Reset

Signal

1.75 — 2.1 V —

DC17 S

VDD VDD Rise Rate

to Ensure Internal Power-on Reset

Signal

0.00005 — 0.115 V/μs—

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. Refer to

parameter BO10 in Table 4-7 for BOR values.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

SSC7150-ML-AB0

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