SSC7150
DS00001885A-page 22 2015 Microchip Technology Inc.
TABLE 4-11: I
2
C BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ T
A ≤ +85°C
Param.
No.
Symbol Characteristics Min.
(1)
Max. Units Conditions
IM10 T
LO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) — μs—
400 kHz mode T
PB * (BRG + 2) — μs
IM11 T
HI:SCL Clock High Time 100 kHz mode TPB * (BRG + 2) — μs—
400 kHz mode TPB * (BRG + 2) — μs
IM20 T
F:SCL I2C_DAx and
I2C_CLx
Fall Time
100 kHz mode — 300 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
IM21 T
R:SCL I2C_DAx and
I2C_CLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
IM25 T
SU:DAT Data Input
Setup Time
100 kHz mode 250 — ns —
400 kHz mode 100 — ns
IM26 T
HD:DAT Data Input
Hold Time
100 kHz mode 0 — μs—
400 kHz mode 0 0.9 μs
IM30 T
SU:STA Start Condition
Setup Time
100 kHz mode TPB * (BRG + 2) — μs Only relevant for
Repeated Start
condition
400 kHz mode TPB * (BRG + 2) — μs
IM31 THD:STA Start Condition
Hold Time
100 kHz mode TPB * (BRG + 2) — μs After this period, the
first clock pulse is
generated
400 kHz mode TPB * (BRG + 2) — μs
IM33 TSU:STO Stop Condition
Setup Time
100 kHz mode TPB * (BRG + 2) — μs—
400 kHz mode TPB * (BRG + 2) — μs
IM34 T
HD:STO Stop Condition
Hold Time
100 kHz mode TPB * (BRG + 2) — ns —
400 kHz mode T
PB * (BRG + 2) — ns
IM40 TAA:SCL Output Valid
from Clock
100 kHz mode — 3500 ns —
400 kHz mode — 1000 ns
IM45 T
BF:SDA Bus Free Time 100 kHz mode 4.7 — μs The amount of time
the bus must be free
before a new
transmission can start
400 kHz mode 1.3 — μs
IM50 C
B Bus Capacitive Loading — 400 pF —
IM51 T
PGD Pulse Gobbler Delay 52 312 ns See Note 2
Note 1: BRG is the value of the I
2
C™ Baud Rate Generator.
2: The typical value for this parameter is 104 ns.
