2015 Microchip Technology Inc. DS00001885A-page 19
SSC7150
4.2 AC Characteristics and Timing Parameters
The information contained in this section defines SSC7150 AC characteristics and timing parameters.
FIGURE 4-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
FIGURE 4-2: POWER-ON RESET TIMING CHARACTERISTICS
TABLE 4-9: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C
Param.
No.
Symbol Characteristics Min. Typical
(1)
Max. Units Conditions
DO56 C
IO All I/O pins 50 pF
DO58 C
B I2C_DAx, I2C_CLx 400 pF In I
2
C™ mode
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from
BOR (V
DD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
VDD/2
CL
RL
Pin
Pin
V
SS
VSS
CL
RL=464Ω
C
L=50 pF for all pins
Load Condition 1
– for all pins except OSC2 Load Condition 2
– for OSC2
Internal Voltage Regulator Enabled
VDD
VPOR
SY00
Power-up Sequence
(Note 2)
Internal Voltage Regulator Enabled
(TPU)
(T
SYSDLY)
CPU Starts Fetching Code
(Note 1)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
SY02
SSC7150
DS00001885A-page 20 2015 Microchip Technology Inc.
FIGURE 4-3: EXTERNAL RESET TIMING CHARACTERISTICS
TABLE 4-10: RESET TIMING
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C
Param.
No.
Symbol Characteristics
(1)
Min. Typical
(2)
Max. Units Conditions
SY00 T
PU Power-up Period
Internal Voltage Regulator
Enabled
—400600μs—
SY02 Tsysdly System Delay Period:
Time Required to Reload Device
Configuration Fuses plus
SYSCLK
(3)
Delay before First
instruction is Fetched.
1 μs +
8 SYSCLK
cycles
——
SY20 Tmclr MCLR# Pulse Width (low) 2 μs—
SY30 T
BOR BOR Pulse Width (low) 1 μs—
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
3: SYSCLK is 48MHz
MCLR#
(SY20)
BOR
(SY30)
TMCLR
TBOR
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
(T
SYSDLY)
SY02
2015 Microchip Technology Inc. DS00001885A-page 21
SSC7150
FIGURE 4-4: I
2
Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
FIGURE 4-5: I
2
Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
I2C_CLx
I2C_DAx
Start
Condition
Stop
Condition
Note: Refer to Figure 4-1 for load conditions.
IM30
IM31
IM34
IM33
IM11
IM10 IM33
IM11
IM10
IM20
IM26
IM25
IM40
IM40
IM45
IM21
I2C_CLx
I2C_DAx
In
I2C_DAx
Out
Note: Refer to Figure 4-1 for load conditions.

SSC7150-ML-AB0

Mfr. #:
Manufacturer:
Microchip Technology
Description:
Sensor Interface Motion Coprocessor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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