2
AT45DB1282
2472C–DFLSH–11/03
applications. This device utilizes Atmel’s e
-
STAC
™
Multi-Level Cell (MLC) memory
technology, which allows a single cell to store two bits of information delivering a
very cost effective high density Flash memory. The AT45DB1282 supports RapidS
serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for
frequencies up to 33 MHz. The dual-interface allows a dedicated serial interface to be
connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller
or vice versa. However, the use of either interface is purely optional. Its 138,412,032 bits
of memory are organized as 16,384 pages of 1,056 bytes each. In addition to the 132-
megabit main memory, the AT45DB1282 also contains two SRAM buffers of 1,056
bytes each. The buffers allow the receiving of data while a page in the main Memory is
being reprogrammed, as well as writing a continuous data stream. EEPROM emulation
(bit or byte alterability) is easily handled with a self-contained three step read-modify-
write operation. Unlike conventional Flash memories that are accessed randomly with
multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial
interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequen-
tial access dramatically reduces active pin count, facilitates hardware layout, increases
system reliability, minimizes switching noise, and reduces package size. The device is
optimized for use in many commercial and industrial applications where high-density,
low-pin count, low-voltage and low-power are essential. The device operates at clock
frequencies up to 40 MHz with a typical active read current consumption of 10 mA.
To allow for simple in-system reprogrammability, the AT45DB1282 does not require
high input voltages for programming. The device operates from a single power supply,
2.7V to 3.6V, for both the program and read operations. The AT45DB1282 is enabled
through the chip select pin (CS
) and accessed via a three-wire interface consisting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or an 8-bit interface
consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK).
All programming and erase cycles are self-timed.
Block Diagram
Memory Array
To provide optimal flexibility, the memory array of the AT45DB1282 is divided into three
levels of granularity comprising of sectors, blocks, and pages. The “Memory Architec-
ture Diagram” illustrates the breakdown of each level and details the number of pages
per sector and block. All program operations to the DataFlash occur on a page by page
basis. The erase operations can be performed at the block or page level.
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
SCK/CLK
CS
RESET
VCC
GND
RDY/BUSY
SER/BYTE
WP
SOSI
I/O7 - I/O0
