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AT45DB1282-TC

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19
AT45DB1282
2472C–DFLSH–11/03
Reset Timing
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations
(Except Status Register Read, Manufacturer and Device ID Read)
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
CS
SCK/CLK
RESET
SO or I/O7 - I/O0
(OUTPUT)
HIGH IMPEDANCE HIGH IMPEDANCE
SI or I/O7 - I/O0
(INPUT)
t
RST
t
REC
t
CSS
SI or I/O7 - I/O0
(INPUT)
CMD 8 bits
8 bits
8 bits
MSB
7 Bits Don't
Care
Page Address
(PA13 - PA0)
X X X X X X X X X X X X X X X X LSB
X X X X X X X X
8 bits
X X X X X X X X
Byte/Buffer Address
(BA10 - BA0/BFA10 - BFA0)
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
SI
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 1
WRITE
BUFFER 2
WRITE
I/O7 - I/O0
20
AT45DB1282
2472C–DFLSH–11/03
Buffer Write
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
SI or I/O7 - I/O0
(INPUT)
CMD
X
X···X, BFA10-8
BFA7-0
n
n+1
Last Byte
· Completes writing into selected buffer
CS
X
SI or I/O7 - I/O0
(INPUT)
CMD
XXXXXXX PA13 PA12-5
CS
Starts self-timed erase/program operation
X···X
PA4-0, XXX
Each transition
represents 8 bits
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
MAIN MEMORY
PAGE TO
BUFFER 1
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE READ
BUFFER 1
READ
BUFFER 2
READ
SO
I/O7 - I/O0
n = 1st byte
n+1 = 2nd byte
21
AT45DB1282
2472C–DFLSH–11/03
Main Memory Page Read
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Buffer Read
SI or I/O7 - I/O0
(INPUT)
CMD
xxx...PA13
PA12-5
BA7-0
X
X
CS
n n+1
SO or I/O7 - I/O0
(OUTPUT)
PA4-0, BA10-8
24 Cycles for Serial
19 Cycles for Parallel
Starts reading page data into buffer
SI or I/O7 - I/O0
(INPUT)
CMD
XX...PA13
PA12-5
X
CS
SO or I/O7 - I/O0
(OUTPUT)
PA4-0, XXX
I/O7-I/O0
(INPUT)
CMD
X
X···X, BFA10-8
BFA7-0
CS
n n+1
I/O7-I/O0
(OUTPUT)
X
ADDR
ADDR
X
1 Dummy Byte (Serial)
2 Dummy Bytes (Parallel)
Each transition
represents 8 bits
n = 1st byte read
n+1 = 2nd byte read
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

AT45DB1282-TC

Mfr. #:
Buy AT45DB1282-TC
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 128M bit
Lifecycle:
New from this manufacturer.
Delivery:
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