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AT45DB1282
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If a Group A mode is in progress (not fully completed), then another mode in Group A
should not be started. However, during this time in which a Group A mode is in
progress, modes in Group B can be started, except the first two Group A commands
(Memory Array Read Commands).
This gives the DataFlash the ability to virtually accommodate a continuous data stream.
While data is being programmed into main memory from buffer 1, data can be loaded
into buffer 2 (or vice versa). See application note AN-4 (“Using Atmels Serial
DataFlash”) for more details.
Pin Descriptions SERIAL/8-BIT INTERFACE CONTROL (SER/BYTE): The DataFlash may be config-
ured to utilize either its serial port or 8-bit port through the use of the serial/8-bit control
pin (SER/BYTE
). When the SER/BYTE pin is held high, the serial port (SI and SO) of
the DataFlash will be used for all data transfers, and the 8-bit port (I/O7 - I/O0) will be in
a high impedance state. Any data presented on the 8-bit port while SER/BYTE
is held
high will be ignored. When the SER/BYTE
is held low, the 8-bit port will be used for all
data transfers, and the SO pin of the serial port will be in a high impedance state. While
SER/BYTE
is low, any data presented on the SI pin will be ignored. Switching between
the serial port and 8-bit port should only be done while the CS
pin is high and the device
is not busy in an internally self-timed operation.
The SER/BYTE
pin is internally pulled high; therefore, if the 8-bit port is never to be
used, then connection of the SER/BYTE
pin is not necessary. In addition, if the
SER/BYTE
pin is not connected or if the SER/BYTE pin is always driven high externally,
then the 8-bit input/output pins (I/O7-I/O0), the VCCP pin, and the GNDP pin should be
treated as “don’t connects”.
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data serially into
the device. The SI pin is used for all data input, including opcodes and address
sequences. If the SER/BYTE
pin is always driven low, then the SI pin should be a “don’t
connect”.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data seri-
ally out from the device. If the SER/BYTE
pin is always driven low, then the SO pin
should be a “don’t connect”.
8-BIT INPUT/OUTPUT (I/O7-I/O0): The I/O7-I/O0 pins are bidirectional and used to
clock data into and out of the device. The I/O7-I/O0 pins are used for all data input,
including opcodes and address sequences. The use of these pins is optional, and the
pins should be treated as “don’t connects” if the SER/BYTE
pin is not connected or if the
SER/BYTE
pin is always driven high externally.
SERIAL CLOCK/CLOCK (SCK/CLK): The SCK and CLK pins are input-only pins and
are used to control the flow of data to and from the DataFlash. The SCK and CLK pins
are used for serial and 8-bit interface respectively. Data is always clocked into the
device on the rising edge of SCK/CLK and clocked out of the device on the falling edge
of SCK/CLK.
CHIP SELECT (CS
): The DataFlash is selected when the CS pin is low. When the
device is not selected, data will not be accepted on the input pins (SI or I/O7-I/O0), and
the output pins (SO or I/O7-I/O0) will remain in a high impedance state. A high-to-low
transition on the CS
pin is required to start an operation, and a low-to-high transition on
the CS
pin is required to end an operation.
HARDWARE PAGE WRITE PROTECT: If the WP
pin is held low, the first 256 pages
(sectors 0 and 1) of the main memory cannot be reprogrammed. The only way to repro-
gram the first 256 pages is to first drive the protect pin high and then use the program
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AT45DB1282
2472C–DFLSH–11/03
commands previously mentioned. If this pin and feature are not utilized it is recom-
mended that the WP
pin be driven high externally.
RESET
: A low state on the reset pin (RESET) will terminate the operation in progress
and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET
pin. Normal operation can
resume once the RESET
pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions
on the RESET
pin during power-on sequences. If this pin and feature are not utilized it is
recommended that the RESET
pin be driven high externally.
READY/BUSY
: This open drain output pin will be driven low when the device is busy in
an internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operations, and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
8-BIT PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP pins are
used to supply power for the 8-bit input/output pins (I/O7-I/O0). The VCCP and GNDP
pins need to be used if the 8-bit port is to be utilized; however, these pins should be
treated as “don’t connects” if the SER/BYTE
pin is not connected or if the SER/BYTE pin
is always driven high externally.
Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the
device will default to Mode 3. In addition, the output pins (SO or I/O7 - I/O0) will be in a
high impedance state, and a high-to-low transition on the CS
pin will be required to start
a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every
falling edge of CS
by sampling the inactive clock state. After power is applied and V
CC
is
at the minimum datasheet value, the system should wait 20 ms before an operational
mode is started.
System
Considerations
The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip
select CS
pins. The sequential 8-bit Rapid8 is controlled by the clock CLK, 8 I/Os and
chip select CS
pins. These signals must rise and fall monotonically and be free from
noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges
and cause improper operation of the device. The PC board traces must be kept to a
minimum distance or appropriately terminated to ensure proper operation. If necessary,
decoupling capacitors can be added on these pins to provide filtering against noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more
important. A key element of any voltage regulation scheme is its current sourcing capa-
bility. Like all Flash memories, the peak current for DataFlash occur during the
programming and erase operation. The regulator needs to supply this peak current
requirement. An under specified regulator can cause current starvation. Besides
increasing system noise, current starvation during programming or erase can lead to
improper operation and possible data corruption.
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Note: 1. The Security Register Program command utilizes data stored in Buffer 1. Therefore,
this command must be used in conjunction with the Buffer 1 write command. See the
Security Register description for details.
Table 1. Read Commands
Command Serial/8-bit Opcode
Main Memory Page Read Both D2h
Continuous Array Read Both E8h
Buffer 1 Read Serial D4h
Buffer 2 Read Serial D6h
Buffer 1 Read 8-bit 54h
Buffer 2 Read 8-bit 56h
Table 2. Program and Erase Commands
Command Serial/8-bit Opcode
Buffer 1 Write Both 84h
Buffer 2 Write Both 87h
Buffer 1 to Main Memory Page Program Both 88h
Buffer 1 to Main Memory Page Program,
Fast Program
Both 98h
Buffer 2 to Main Memory Page Program Both 89h
Buffer 2 to Main Memory Page Program,
Fast Program
Both 99h
Page Erase Both 81h
Block Erase Both 50h
Table 3. Additional Commands
Command Serial/8-bit Opcode
Main Memory Page to Buffer 1 Transfer Both 53h
Main Memory Page to Buffer 2 Transfer Both 55h
Main Memory Page to Buffer 1 Compare Both 60h
Main Memory Page to Buffer 2 Compare Both 61h
Status Register Read Both D7h
Manufacturer and Device ID Read Serial 9Fh
Security Register Program
(1)
Both 9Ah
Security Register Read Both 77h

AT45DB1282-TC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 128M bit
Lifecycle:
New from this manufacturer.
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