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Product data sheet Rev. 4 — 5 December 2014 16 of 48
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PCA8565
Real time clock/calendar
[1] Default value.
[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to
1
60
Hz for power saving.
8.7.2 Register Countdown_Timer
The timer register is an 8-bit binary countdown timer. It is enabled or disabled via the
Timer_control register. The source clock for the timer is also selected by the Timer_control
register. Other timer properties such as single or periodic interrupt generation are
controlled via the register Control_status_2 (address 01h).
For accurate read back of the count down value, it is recommended to read the register
twice and check for consistent results, since it is not possible to freeze the countdown
timer counter during read back.
8.8 Register CLKOUT_control and clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
CLKOUT_control register at address 0Dh. Frequencies of 32.768 kHz (default),
1.024 kHz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller
clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain
output and enabled at power-on. If disabled it becomes high-impedance.
Table 23. Register Timer_control (address 0Eh) bits description
Bit Symbol Value Description
7TE 0
[1]
timer is disabled
1 timer is enabled
6 to 2 - - unused
1 to 0 TD[1:0] timer source clock frequency select
[2]
00 4.096 kHz
01 64 Hz
10 1 Hz
11
[2] 1
60
Hz
Table 24. Timer (address 0Fh) bits description
Bit Symbol Value Description
7 to 0 COUNTDOWN_TIMER 00h to FFh countdown period in seconds:
where n is the countdown value
Table 25. Timer register bits value range
Bit
7 6 5 4 3 2 1 0
1286432168421
CountdownPeriod
n
SourceClockFrequency
---------------------------------------------------------------
=
PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 17 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
[1] Default value.
8.9 Interrupt output
8.9.1 Bits TF and AF
When an alarm occurs, AF is set to 1. Similarly, at the end of a timer countdown, TF is
set to 1. These bits maintain their value until overwritten by command. If both timer and
alarm interrupts are required in the application, the source of the interrupt is determined
by reading these bits.
Table 26. Register CLKOUT_control (address 0Dh) bits description
Bit Symbol Value Description
7 FE 0 the CLKOUT output is inhibited and CLKOUT output is set
to high-impedance
1
[1]
the CLKOUT output is activated
6 to 2 - - unused
1 to 0 FD[1:0] frequency output at pin CLKOUT
00
[1]
32.768 kHz
01 1.024 kHz
10 32 Hz
11 1 Hz
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 8. AF timing
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PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 18 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
8.9.1.1 Clearing the alarm flag (AF)
Table 28
shows an example for clearing bit AF but leaving bit TF unaffected. Clearing the
flags is made by a write command; therefore bits 7, 6, 4, 1 and 0 must be written with their
previous values. Repeatedly re-writing these bits has no influence on the functional
behavior.
To prevent the timer flags being overwritten while clearing AF, a logical AND is performed
during a write access. Writing a logic 1 will cause the flag to maintain its value, whereas
writing a logic 0 will cause the flag to be reset.
The following table shows what instruction must be sent to clear bit AF. In this example bit
TF is unaffected.
8.9.2 Bits TIE and AIE
These bits activate or deactivate the generation of an interrupt when TF or AF is asserted
respectively. The interrupt is the logical OR of these two conditions when both AIE and
TIE are set.
When bits TIE and AIE are disabled, pin INT will remain high-impedance.
Fig 9. Interrupt scheme
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Table 27. Flag location in register Control_2
Register Bit
7 6 5 4 3 2 1 0
Control_2----AFTF--
Table 28. Example to clear only AF (bit 3) in register Control_2
Register Bit
7 6 5 4 3 2 1 0
Control_2----01--

PCA8565BS/1,118

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IC RTC CLK/CALENDAR I2C 10-HVSON
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