PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 31 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
V
DD
= 3 V; Timer = 1 minute; CLKOUT = 32 kHz. T
amb
=25C; normalized to V
DD
=3V.
Fig 24. I
DD
as a function of temperature Fig 25. Frequency deviation as a function of V
DD
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PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 32 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
14. Dynamic characteristics
[1] Integrated load capacitance, C
L(itg)
, is a calculation of C
OSCI
and C
OSCO
in series.
[2] For f
CLKOUT
= 1.024 kHz, 32 Hz and 1 Hz.
[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to V
IL
and V
IH
with an input voltage
swing of V
SS
to V
DD
.
[4] A detailed description of the I
2
C-bus specification is given in the document Ref. 12 “UM10204.
[5] I
2
C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
Table 33. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +125
C; f
osc
= 32.768 kHz; quartz R
s
=40k
; C
L
= 8 pF; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
Oscillator
C
L(itg)
integrated load capacitance
[1]
15 25 35 pF
f
osc
/f
osc
relative oscillator frequency variation V
DD
=200mV;
T
amb
=25C
-0.2-ppm
Quartz crystal parameters (f = 32.768 kHz)
R
s
series resistance - - 100 k
C
L
load capacitance - 10 - pF
C
trim
trimmer capacitance 5 - 25 pF
CLKOUT output
CLKOUT
duty cycle on pin CLKOUT
[2]
-50-%
I
2
C-bus timing characteristics
[3][4]
f
SCL
SCL clock frequency
[5]
- - 400 kHz
t
HD;STA
hold time (repeated) START condition 0.6 - - s
t
SU;STA
set-up time for a repeated START
condition
0.6 - - s
t
LOW
LOW period of the SCL clock 1.3 - - s
t
HIGH
HIGH period of the SCL clock 0.6 - - s
t
r
rise time of both SDA and SCL signals - - 0.3 s
t
f
fall time of both SDA and SCL signals - - 0.3 s
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
t
BUF
bus free time between a STOP and
START condition
4.7 - - s
t
SU;STO
set-up time for STOP condition 0.6 - - s
t
SP
pulse width of spikes that must be
suppressed by the input filter
--50ns
C
b
capacitive load for each bus line - - 400 pF
C
Litg
C
OSCI
C
OSCO

C
OSCI
C
OSCO
+
--------------------------------------------
=
PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 33 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
15. Application information
Fig 26. I
2
C-bus timing waveforms
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PCA8565BS/1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC RTC CLK/CALENDAR I2C 10-HVSON
Lifecycle:
New from this manufacturer.
Delivery:
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