PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 8 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
8.3 Reset
The PCA8565 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I
2
C-bus logic is initialized including the address pointer. All
other registers are set according to Table 8
.
[1] Registers labeled ‘x’ are undefined at power-on and unchanged by subsequent resets.
8.3.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I
2
C-bus pins, SDA and SCL, be toggled in a specific order as
shown in Figure 3
. All timings are required minimums.
Once the override mode has been entered, the device immediately stops being reset and
normal operation may commence i.e. entry into the EXT_CLK test mode via I
2
C-bus
access. The override mode may be cleared by writing a logic 0 to TESTC. TESTC must
be set to logic 1 before re-entry into the override mode is possible. Setting TESTC to
logic 0 during normal operation has no effect except to prevent entry into the POR
override mode.
Table 8. Register reset values
[1]
Address Register name Bit
7 6 5 4 3 2 1 0
00h Control_1 00001000
01h Control_2 xx000000
02hSeconds 1xxxxxxx
03hMinutes 1xxxxxxx
04hHours xxxxxxxx
05hDays xxxxxxxx
06hWeekdays xxxxxxxx
07hMonths_centuryxxxxxxxx
08hYears xxxxxxxx
09hMinute_alarm 1xxxxxxx
0AhHour_alarm 1xxxxxxx
0BhDay_alarm 1xxxxxxx
0ChWeekday_alarm1xxxxxxx
0DhCLKOUT_control1xxxxx00
0EhTimer_control 0xxxxx11
0FhTimer xxxxxxxx
