DS1972
1024-Bit EEPROM i
Button
________________________________________________________________
Maxim Integrated Products
1
19-4888; Rev 4; 1/12
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The DS1972 is a 1024-bit, 1-Wire
®
EEPROM chip orga-
nized as four memory pages of 256 bits each in a
rugged iButton
®
package. Data is written to an 8-byte
scratchpad, verified, and then copied to the EEPROM
memory. As a special feature, the four memory pages
can individually be write protected or put in EPROM-
emulation mode, where bits can only be changed from
a 1 to a 0 state. The DS1972 communicates over the
single-conductor 1-Wire bus. The communication fol-
lows the standard 1-Wire protocol. Each device has its
own unalterable and unique 64-bit ROM registration
number that is factory lasered into the device. The reg-
istration number is used to address the device in a mul-
tidrop, 1-Wire net environment.
Applications
Access Control/Parking Meter
Work-in-Progress Tracking
Tool Management
Inventory Control
Maintenance/Inspection Data Storage
Features
1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 Bits
Individual Memory Pages Can Be Permanently
Write Protected or Put in EPROM-Emulation Mode
(“Write to 0”)
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
IEC 1000-4-2 Level 4 ESD Protection (±8kV
Contact, ±15kV Air, Typical)
Reads and Writes Over a Wide Voltage Range
from 2.8V to 5.25V from -40°C to +85°C
Communicates to Host with a Single Digital
Signal at 15.4kbps or 125kbps Using 1-Wire
Protocol
Common iButton Features
Unique Factory-Lasered 64-Bit Registration
Number Ensures Error-Free Device Selection and
Absolute Traceability Because No Two Parts are
Alike
Built-In Multidrop Controller for 1-Wire Net
Chip-Based Data Carrier Stores Digital
Identification and Information, Armored in a
Durable Stainless-Steel Case
Data Can Be Accessed While Affixed to Object
Button Shape is Self-Aligning with Cup-Shaped
Probes
Easily Affixed with Self-Stick Adhesive Backing,
Latched by its Flange, or Locked with a Ring
Pressed Onto its Rim
Presence Detector Acknowledges When Reader
First Applies Voltage
Ordering Information
16.25mm
5.89mm
0.51mm
3.10mm
0.51mm
17.35mm
BRANDING
F5 SIZE
GND
GND
IOIO
F3 SIZE
52 2D
0000006234FB
1-Wire
®
®
i
B
u
t
t
o
n
®
.
c
o
m
Y
Y
W
W
Z
Z
Z
D
S
1
9
7
2
-
F
5
Pin Configurations
+
Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
DS1972-F5+ -40°C to +85°C F5 i
Button
DS1972-F3+ -40°C to +85°C F3 iButton
Examples of Accessories
PART ACCESSORY
DS9096P Self-Stick Adhesive Pad
DS9101 Multipurpose Clip
DS9093RA Mounting Lock Ring
DS9093A Snap-In Fob
DS9092 iButton Probe
1-Wire and i
Button are registered trademarks of Maxim
Integrated Products, Inc.
DS1972
1024-Bit EEPROM i
Button
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IO Voltage Range to GND .......................................-0.5V to +6V
IO Sink Current ...................................................................20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage V
PUP
(Note 2) 2.8 5.25 V
1-Wire Pullup Resistance R
PUP
(Notes 2, 3) 0.3 2.2 k
Input Capacitance C
IO
(Notes 4, 5) 1000 pF
Input Load Current I
L
IO pin at V
PUP
0.05 6.7 μA
High-to-Low Switching Threshold V
TL
(Notes 5, 6, 7) 0.5
V
PUP
-
1.8
V
Input Low Voltage V
IL
(Notes 2, 8) 0.5 V
Low-to-High Switching Threshold V
TH
(Notes 5, 6, 9) 1.0
V
PUP
-
1.0
V
Switching Hysteresis V
HY
(Notes 5, 6, 10) 0.21 1.70 V
Output Low Voltage V
OL
At 4mA (Note 11) 0.4 V
Standard speed, R
PUP
= 2.2k 5
Overdrive speed, R
PUP
= 2.2k 2
Recovery Time
(Notes 2, 12)
t
REC
Overdrive speed, directly prior to reset
pulse; R
PUP
= 2.2k
5
μs
Standard speed 0.5 5.0
Rising-Edge Hold-Off Time
(Notes 5, 13)
t
REH
Overdrive speed Not applicable (0)
μs
Standard speed 65
Time Slot Duration
(Notes 2, 14)
t
SLOT
Overdrive speed 8
μs
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed 480 640
Reset Low Time (Note 2) t
RSTL
Overdrive speed 48 80
μs
Standard speed 15 60
Presence-Detect High Time t
PDH
Overdrive speed 2 6
μs
Standard speed 60 240
Presence-Detect Low Time t
PDL
Overdrive speed 8 24
μs
Standard speed 60 75
Presence-Detect Sample Time
(Notes 2, 15)
t
MSP
Overdrive speed 6 10
μs
DS1972
1024-Bit EEPROM i
Button
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: 1-Wire WRITE
Standard speed 60 120
Overdrive speed, V
PUP
> 4.5V 5 15.5
Write-Zero Low Time
(Notes 2, 16, 17)
t
W0L
Overdrive speed 6 15.5
μs
Standard speed 1 15
Write-One Low Time
(Notes 2, 17)
t
W1L
Overdrive speed 1 2
μs
IO PIN: 1-Wire READ
Standard speed 5 15 -
Read Low Time
(Notes 2, 18)
t
RL
Overdrive speed 1 2 -
μs
Standard speed t
RL
+ 15
Read Sample Time
(Notes 2, 18)
t
MSR
Overdrive speed t
RL
+ 2
μs
EEPROM
Programming Current I
PROG
(Notes 5, 19) 0.8 mA
Programming Time t
PROG
(Note 20) 10 ms
At +25°C 200k
Write/Erase Cycles (Endurance)
(Notes 21, 22)
N
CY
At +85°C (worst case) 50k
Data Retention
(Notes 23, 24, 25)
t
DR
At +85°C (worst case) 40 Years
Note 1: Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and rel-
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4: Maximum value represents the internal parasite capacitance when V
PUP
is first applied. If a 2.2kΩ resistor is used to pull
up the data line, 2.5µs after V
PUP
has been applied, the parasite capacitance does not affect normal communications.
Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6: V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of
V
TL
, V
TH
, and V
HY
.
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to V
ILMAX
at all times the master is driving IO to a logic 0 level.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to t
W0LMIN
+ t
RECMIN
.
Note 15: Interval after t
RSTL
during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS1972 present.
Minimum limit is t
PDHMAX
; maximum limit is t
PDHMIN
+ t
PDLMIN
.
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the
Comparison Table
.
Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.

DS1972-F3+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
iButtons & Accessories 1024-Bit EEPROM iButton
Lifecycle:
New from this manufacturer.
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