DS1972-F3+ Datasheet DS1972-F5+, DS1972-F3+ | P4-P6

DS1972

1024-Bit EEPROM i

Button

4 _______________________________________________________________________________________

Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval

should be such that the voltage at IO is greater than or equal to V

PUPMIN

. If V

PUP

in the system is close to V

PUPMIN

, a low-

impedance bypass of R

PUP

, which can be activated during programming, may need to be added.

Note 20: Interval begins t

REHMAX

after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad

sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by

the device has returned from I

PROG

to I

Note 21: Write-cycle endurance is degraded as T

increases.

Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 23: Data retention is degraded as T

increases.

Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.

COMPARISON TABLE

LEGACY VALUES DS1972 VALUES

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

PARAMETER

MIN MAX MIN MAX MIN MAX MIN MAX

SLOT

(including t

REC

) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined)

RSTL

480 (undefined) 48 80 480 640 48 80

PDH

15 60 2 6 15 60 2 6

PDL

60 240 8 24 60 240 8 24

W0L

60 120 6 16 60 120 6 15.5

Intentional change; longer recovery time requirement due to modified 1-Wire front-end.

Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.

DS1972

1024-Bit EEPROM i

Button

_______________________________________________________________________________________ 5

Detailed Description

The DS1972 combines 1024 bits of EEPROM, an

8-byte register/control page with up to 7 user read/write

bytes, and a fully featured 1-Wire interface in a rugged

iButton package. Each DS1972 has its own 64-bit ROM

registration number that is factory lasered into the chip

to provide a guaranteed unique identity for absolute

traceability. Data is transferred serially through the 1-

Wire protocol, which requires only a single data contact

and a ground return. The DS1972 has an additional

memory area called the scratchpad that acts as a

buffer when writing to the main memory or the register

page. Data is first written to the scratchpad from which

it can be read back. After the data has been verified, a

Copy Scratchpad command transfers the data to its

final memory location. Applications of the DS1972

include access control/parking meter, work-in-progress

tracking, tool management, inventory control, and

maintenance/inspection data storage. Free software for

communication with the DS1972 is available at

www.maxim-ic.com/ibutton.

Overview

The block diagram in Figure 1 shows the relationships

between the major control and memory sections of the

DS1972. The DS1972 has four main data components:

64-bit lasered ROM, 64-bit scratchpad, four 32-byte

pages of EEPROM, and a 64-bit register page.

The hierarchical structure of the 1-Wire protocol is

shown in Figure 2. The bus master must first provide

one of the seven ROM function commands: Read

ROM, Match ROM, Search ROM, Skip ROM, Resume,

Overdrive-Skip ROM, or Overdrive-Match ROM. Upon

completion of an Overdrive-Skip ROM or Overdrive-

Match ROM command byte executed at standard

speed, the device enters overdrive mode where all

subsequent communication occurs at a higher

speed. The protocol required for these ROM function

MEMORY

FUNCTION

CONTROL UNIT

DATA MEMORY

4 PAGES OF

256 BITS EACH

CRC-16

GENERATOR

64-BIT

SCRATCHPAD

1-Wire

FUNCTION CONTROL

64-BIT

LASERED ROM

PARASITE POWER

64 BITS

DS1972

Figure 1. Block Diagram

DS1972 COMMAND LEVEL:

AVAILABLE COMMANDS: DATA FIELD AFFECTED:

READ ROM

MATCH ROM

SEARCH ROM

SKIP ROM

RESUME

OVERDRIVE-SKIP ROM

OVERDRIVE-MATCH ROM

64-BIT REG. #, RC-FLAG

RC-FLAG

RC-FLAG, OD-FLAG

64-BIT REG. #, RC-FLAG, OD-FLAG

1-Wire ROM FUNCTION COMMANDS

(SEE FIGURE 9)

WRITE SCRATCHPAD

READ SCRATCHPAD

COPY SCRATCHPAD

READ MEMORY

64-BIT SCRATCHPAD, FLAGS

64-BIT SCRATCHPAD

DATA MEMORY, REGISTER PAGE

DS1972-SPECIFIC

MEMORY FUNCTION COMMANDS

(SEE FIGURE 7)

Figure 2. Hierarchical Structure for 1-Wire Protocol

DS1972

1024-Bit EEPROM i

Button

6 _______________________________________________________________________________________

1ST

STAGE

2ND

STAGE

3RD

STAGE

4TH

STAGE

7TH

STAGE

8TH

STAGE

6TH

STAGE

5TH

STAGE

POLYNOMIAL = X

+ X

+ 1

INPUT DATA

Figure 4. 1-Wire CRC Generator

commands is described in Figure 9. After a ROM

function command is successfully executed, the

memory functions become accessible and the master

can provide any one of the four memory function

commands. The protocol for these memory function

commands is described in Figure 7. All data is read

and written least significant bit first.

64-Bit Lasered ROM

Each DS1972 contains a unique ROM code that is 64

bits long. The first 8 bits are a 1-Wire family code. The

next 48 bits are a unique serial number. The last 8 bits

are a cyclic redundancy check (CRC) of the first 56 bits.

See Figure 3 for details. The 1-Wire CRC is generated

using a polynomial generator consisting of a shift regis-

ter and XOR gates as shown in Figure 4. The polynomial

is X

+ X

+ 1. Additional information about the

1-Wire CRC is available in Application Note 27:

Understanding and Using Cyclic Redundancy Checks

with Maxim i

Button Products

The shift register bits are initialized to 0. Then, starting

with the least significant bit of the family code, one bit

at a time is shifted in. After the 8th bit of the family code

has been entered, the serial number is entered. After

the last bit of the serial number has been entered, the

shift register contains the CRC value. Shifting in the 8

bits of the CRC returns the shift register to all 0s.

MSB

8-BIT

CRC CODE

48-BIT SERIAL NUMBER

MSB MSBLSB

LSB

8-BIT FAMILY CODE

(2Dh)

MSBLSB

Figure 3. 64-Bit Lasered ROM

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

DS1972-F3+

Mfr. #:

Buy DS1972-F3+

Manufacturer:

Maxim Integrated

Description:

iButtons & Accessories 1024-Bit EEPROM iButton

Lifecycle:

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DS1972-F3+

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