DS1972
1024-Bit EEPROM i
Button
16 ______________________________________________________________________________________
Resume [A5h]
To maximize the data throughput in a multidrop envi-
ronment, the Resume command is available. This com-
mand checks the status of the RC bit and, if it is set,
directly transfers control to the memory function com-
mands, similar to a Skip ROM command. The only way
to set the RC bit is through successfully executing the
Match ROM, Search ROM, or Overdrive-Match ROM
command. Once the RC bit is set, the device can
repeatedly be accessed through the Resume com-
mand. Accessing another device on the bus clears the
RC bit, preventing two or more devices from simultane-
ously responding to the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the memory func-
tions without providing the 64-bit ROM code. Unlike the
normal Skip ROM command, the Overdrive-Skip ROM
command sets the DS1972 into the overdrive mode
(OD = 1). All communication following this command
must occur at overdrive speed until a reset pulse of
minimum 480µs duration resets all devices on the bus
to standard speed (OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be
issued followed by a Match ROM or Search ROM com-
mand sequence. This speeds up the time for the
search process. If more than one slave supporting
overdrive is present on the bus and the Overdrive-Skip
ROM command is followed by a read command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-
bit ROM sequence transmitted at overdrive speed
allows the bus master to address a specific DS1972 on
a multidrop bus and to simultaneously set it in overdrive
mode. Only the DS1972 that exactly matches the 64-bit
ROM sequence responds to the subsequent memory
function command. Slaves already in overdrive mode
from a previous Overdrive-Skip ROM or successful
Overdrive-Match ROM command remain in overdrive
mode. All overdrive-capable slaves return to standard
speed at the next reset pulse of minimum 480µs dura-
tion. The Overdrive-Match ROM command can be used
with a single device or multiple devices on the bus.
1-Wire Signaling
The DS1972 requires strict protocols to ensure data
integrity. The protocol consists of four types of signal-
ing on one line: reset sequence with reset pulse and
presence pulse, write-zero, write-one, and read-data.
Except for the presence pulse, the bus master initiates
all falling edges. The DS1972 can communicate at two
different speeds: standard speed and overdrive speed.
If not explicitly set into the overdrive mode, the DS1972
communicates at standard speed. While in overdrive
mode, the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from V
PUP
below the threshold V
TL
. To get
from active to idle, the voltage needs to rise from
V
ILMAX
past the threshold V
TH
. The time it takes for the
voltage to make this rise is seen in Figure 10 as ε, and
its duration depends on the pullup resistor (R
PUP
) used
and the capacitance of the 1-Wire network attached.
The voltage V
ILMAX
is relevant for the DS1972 when
determining a logical level, not triggering any events.
Figure 10 shows the initialization sequence required to
begin any communication with the DS1972. A reset
pulse followed by a presence pulse indicates that the
DS1972 is ready to receive data, given the correct
ROM and memory function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for t
RSTL
+ t
F
to compensate for the
edge. A t
RSTL
duration of 480µs or longer exits the
overdrive mode, returning the device to standard
speed. If the DS1972 is in overdrive mode and t
RSTL
is
no longer than 80µs, the device remains in overdrive
mode. If the device is in overdrive mode and t
RSTL
is
between 80µs and 480µs, the device resets, but the
communication speed is undetermined.
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to V
PUP
through the pullup resistor or, in the case of a DS2482-
x00 or DS2480B driver, through the active circuitry.
When the threshold V
TH
is crossed, the DS1972 waits
for t
PDH
and then transmits a presence pulse by pulling
the line low for t
PDL
. To detect a presence pulse, the
master must test the logical state of the 1-Wire line at
t
MSP
.
The t
RSTH
window must be at least the sum of
t
PDHMAX
, t
PDLMAX
, and t
RECMIN
. Immediately after
t
RSTH
is expired, the DS1972 is ready for data commu-
nication. In a mixed population network, t
RSTH
should
be extended to minimum 480µs at standard speed and
48µs at overdrive speed to accommodate other 1-Wire
devices.
DS1972
1024-Bit EEPROM i
Button
______________________________________________________________________________________ 17
Read/Write Time Slots
Data communication with the DS1972 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 11 illus-
trates the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold V
TL
, the DS1972 starts its internal
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the V
TH
threshold before the write-
one low time t
W1LMAX
is expired. For a write-zero time
slot, the voltage on the data line must stay below the
V
TH
threshold until the write-zero low time t
W0LMIN
is
expired. For the most reliable communication, the volt-
age on the data line should not exceed V
ILMAX
during
the entire t
W0L
or t
W1L
window. After the V
TH
threshold
has been crossed, the DS1972 needs a recovery time
t
REC
before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V
TL
until the read low time t
RL
is expired. During the t
RL
window, when responding with a 0, the DS1972 starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS1972 does not hold the data line low at all, and the
voltage starts rising as soon as t
RL
is over.
The sum of t
RL
+ δ (rise time) on one side and the inter-
nal timing generator of the DS1972 on the other side
define the master sampling window (t
MSRMIN
to
t
MSRMAX
), in which the master must perform a read
from the data line. For the most reliable communication,
t
RL
should be as short as permissible, and the master
should read close to but no later than t
MSRMAX
. After
reading from the data line, the master must wait until
t
SLOT
is expired. This guarantees sufficient recovery
time t
REC
for the DS1972 to get ready for the next time
slot. Note that t
REC
specified herein applies only to a
single DS1972 attached to a 1-Wire line. For multide-
vice configurations, t
REC
must be extended to accom-
modate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482-
x00 or DS2480B 1-Wire line drivers can be used.
RESISTOR MASTER DS1972
t
RSTL
t
PDL
t
RSTH
t
PDH
MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
F
t
REC
t
MSP
Figure 10. Initialization Procedure: Reset and Presence Pulse
DS1972
1024-Bit EEPROM i
Button
18 ______________________________________________________________________________________
RESISTOR MASTER
RESISTOR MASTER
RESISTOR MASTER DS1972
ε
ε
δ
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
t
SLOT
t
W1L
t
REC
t
SLOT
t
SLOT
t
W0L
t
REC
MASTER
SAMPLING
WINDOW
t
RL
t
MSR
WRITE-ONE TIME SLOT
WRITE-ZERO TIME SLOT
READ-DATA TIME SLOT
Figure 11. Read/Write Timing Diagrams

DS1972-F3+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
iButtons & Accessories 1024-Bit EEPROM iButton
Lifecycle:
New from this manufacturer.
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