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AR0134CSSM25SUEAH3-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
AR0134CS
www.onsemi.com
19
Table 15. STANDBY CURRENT CONSUMPTION
(Analog − V
AA
+ V
AA
_PIX + V
DD
_PLL; Digital − V
DD
+ V
DD
_IO; T
A
= 25°C)
Definition
Condition Min Typ Max Unit
Hard Standby (Clock Off, Driven Low)
Analog, 2.8 V – 3 15
mA
Digital, 1.8 V – 25 80
mA
Hard Standby (Clock On, EXTCLK = 20 MHz)
Analog, 2.8 V – 12 25
mA
Digital, 1.8 V – 1.1 1.7 mA
Soft Standby (Clock Off, Driven Low)
Analog, 2.8 V – 3 15
mA
Digital, 1.8 V – 25 80
mA
Soft Standby (Clock On, EXTCLK = 20 MHz)
Analog, 2.8 V – 12 25
mA
Digital, 1.8 V – 1.1 1.7 mA
HiSPi Electrical Specifications
The ON Semiconductor AR0134CS sensor supports
SLVS mode only, and does not have a DLL for timing
adjustments. Refer to the High-Speed Serial Pixel (HiSPi)
Interface Physical Layer Specification v2.00.00 for
electrical definitions, specifications, and timing
information. The V
DD
_SLVS supply in this data sheet
corresponds to V
DD
_TX in the HiSPi Physical Layer
Specification. Similarly, V
DD
is equivalent to V
DD
_HiSPi
as referenced in the specification. The HiSPi transmitter
electrical specifications are listed at 700 MHz.
Table 16. INPUT VOLTAGE AND CURRENT (HiSPi POWER SUPPLY 0.4 V)
(Measurement Conditions: Max Freq. 700 MHz)
Symbol Parameter Min Typ Max Unit
I
DD
_SLVS
Supply Current (PWR
HiSPi
) (Driving 100 W Load)
– 10 15 mA
V
CMD
HiSPi Common Mode Voltage (Driving 100 W Load)
V
DD
_SLVS ×
0.45
V
DD
_SLVS/2 V
DD
_SLVS ×
0.55
V
|V
OD
|
HiSPi Differential Output Voltage (Driving 100 W Load)
V
DD
_SLVS ×
0.36
V
DD
_SLVS/2 V
DD
_SLVS ×
0.64
V
DV
CM
Change in V
CM
between Logic 1 and 0 − − 25 mV
|V
OD
| Change in |V
OD
| between Logic 1 and 0 − − 25 mV
NM V
OD
Noise Margin – − 30 %
|DV
CM
|
Difference in V
CM
between any Two Channels − − 50 mV
|DV
OD
|
Difference in V
OD
between any Two Channels − − 100 mV
DV
CM
_ac
Common-mode AC Voltage (pk) without V
CM
Cap Termina-
tion
− − 50 mV
DV
CM
_ac
Common-mode AC Voltage (pk) with V
CM
Cap Termination − − 30 mV
V
OD
_ac Max Overshoot Peak |V
OD
| − − 1.3 × |V
OD
| V
V
diff_pkpk
Max Overshoot V
diff
pk-pk
− − 2.6 × |V
OD
| V
V
eye
Eye Height 1.4 × V
OD
− −
R
o
Single-ended Output Impedance 35 50 70
W
DR
o
Output Impedance Mismatch − − 20 %
AR0134CS
www.onsemi.com
20
Figure 16. Differential Output Voltage for Clock and Data Pairs
V
DIFFmin
V
DIFFmax
0 V (Diff)
Output Signal
is ‘Cp − Cn’ or
‘Dp − Dn’
Table 17. RISE AND FALL TIMES
(Measurement Conditions: HiSPi Power Supply 0.4 V, Max Freq. 700 MHz)
Symbol
Parameter Min Typ Max Unit
1/UI Data Rate 280 – 700 Mb/s
TxPRE Max Setup Time from Transmitter (Note 17) 0.3 – – UI
TxPost Max Hold Time from Transmitter 0.3 – – UI
RISE Rise Time (20% − 80%) – 0.25 UI –
FALL Fall Time (20% − 80%) 150 ps 0.25 UI –
PLL_DUTY Clock Duty 45 50 55 %
t
pw
Bitrate Period (Note 17) 1.43 − 3.57 ns
t
eye
Eye Width (Notes 17, 18) 0.3 − − UI
t
totaljit
Data Total Jitter (pk pk)@1e−9 (Notes 17, 18) − − 0.2 UI
t
ckjit
Clock Period Jitter (RMS) (Note 18) − − 50 ps
t
cyjit
Clock Cycle to Cycle Jitter (RMS) (Note 18) − − 100 ps
t
chskew
Clock to Data Skew (Notes 17, 18) −0.1 − 0.1 UI
t
|PHYskew|
PHY-to-PHY Skew (Notes 17, 21) − − 2.1 UI
t
DIFFSKEW
Mean Differential Skew (Note 22) –100 − 100 ps
17.One UI is defined as the normalized mean time between one edge and the following edge of the clock.
18.Taken from 0 V crossing point.
19.Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates
so the rise and fall times do not exceed the maximum 0.3 UI.
20.The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
21.The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
22.Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two
complementary edges at mean V
CM
point.
AR0134CS
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21
Figure 17. Eye Diagram for Clock and Data Signals
DATA MASK
CLOCK MASK
Trigger/Reference
UI/2 UI/2
RISE
FALL
V
DIFF
Max V
DIFF
TxPre TxPost
80%
20%
V
DIFF
CLKJITTER
Figure 18. Skew within the PHY and Output Channels
VCMD
t
CMPSKEW
t
CHSKEW1PHY
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AR0134CSSM25SUEAH3-GEVB

Mfr. #:
Buy AR0134CSSM25SUEAH3-GEVB
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 1.2MP 1/3 CIS MONO2
Lifecycle:
New from this manufacturer.
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