AR0134CS
www.onsemi.com
22
POWER-ON RESET AND STANDBY TIMING
Power-Up Sequence
The recommended power-up sequence for the AR0134CS
is shown in Figure 19. The available power supplies
(V
DD
_IO, V
DD
, V
DD
_SLVS, V
DD
_PLL, V
AA
, V
AA
_PIX)
must have the separation specified below.
1. Turn on V
DD
_PLL power supply.
2. After 0−10 ms, turn on V
AA
and V
AA
_PIX power
supply.
3. After 0−10 ms, turn on V
DD
_IO power supply.
4. After the last power supply is stable, enable
EXTCLK.
5. If RESET_BAR is in a LOW state, hold
RESET_BAR LOW for at least 1 ms.
If RESET_BAR is in a HIGH state, assert
RESET_BAR for at least 1 ms.
6. Wait 160000 EXTCLKs (for internal initialization
into software standby).
7. Configure PLL, output, and image settings to
desired values.
8. Wait 1 ms for the PLL to lock.
9. Set streaming mode (R0x301a[2] = 1).
Figure 19. Power Up
EXTCLK
V
DD
_SLVS (0.4)
V
AA
_PIX
V
AA
(2.8)
V
DD
_IO (1.8/2.8)
V
DD
(1.8)
V
DD
_PLL (2.8)
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
X
Hard
Reset
Internal Ini-
tialization
Software
Standby
PLL Clock Streaming
RESET_BAR
Table 18. POWER-UP SEQUENCE
Symbol
Definition Min Typ Max Unit
t
0
V
DD
_PLL to V
AA
/V
AA
_PIX 0 10 –
ms
t
1
V
AA
/V
AA
_PIX to V
DD
_IO 0 10 –
ms
t
2
V
DD
_IO to V
DD
0 10 –
ms
t
3
V
DD
to V
DD
_SLVS 0 10 –
ms
t
X
Xtal Settle Time – 30 (Note 23) – ms
t
4
Hard Reset 1 (Note 24) – – ms
t
5
Internal Initialization 160000 – – EXTCLKs
t
6
PLL Lock Time 1 – – ms
23.Xtal settling time is component-dependent, usually taking about 10–100 ms.
24.Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
25.It is critical that V
DD
_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that V
DD
_PLL is powered after other supplies then the sensor may have functionality issues and will experience
high current draw on this supply.
