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Figure 6. 9 y 9 mm 63-ball iBGA Package
Top View
(Ball Down)
A
B
C
D
E
F
G
H
12345678
V
DD
_PLL
EXTCLK
S
ADDR
LINE_
VALID
D
OUT
8
D
OUT
4
D
OUT
0
SLVSCN
V
DD
_SLVS
S
CLK
FRAME_
VALID
D
OUT
9
D
OUT
5
D
OUT
1
SLVS0N
SLVSCP
(SLVS3N)
S
DATA
PIXCLK
D
OUT
10
D
OUT
6
D
OUT
2
SLVS0P
SLVS2N
(SLVS3P)
D
GND
FLASH
D
OUT
11
D
OUT
7
D
OUT
3
SLVS1N
SLVS2P
D
GND
D
GND
D
GND
D
GND
D
GND
D
GND
SLVS1P
V
DD
V
DD
V
DD
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
V
AA
A
GND
V
AA
_PIX
RESERVED
TEST
TRIGGER
V
DD
_IO
V
DD
V
AA
A
GND
V
AA
_PIX
RESERVED
RESERVED
OE_BAR
RESET_
BAR
STANDBY
Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE
Name iBGA Pin Type Description
SLVS0_N A2 Output HiSPi serial data, lane 0, differential N
SLVS0_P A3 Output HiSPi serial data, lane 0, differential P
SLVS1_N A4 Output HiSPi serial data, lane 1, differential N
SLVS1_P A5 Output HiSPi serial data, lane 1, differential P
STANDBY A8 Input Standby-mode enable pin (active HIGH)
V
DD
_PLL B1 Power PLL power
SLVSC_N B2 Output HiSPi serial DDR clock differential N
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Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE (continued)
Name DescriptionTypeiBGA Pin
SLVSC_P B3 Output HiSPi serial DDR clock differential P
SLVS2_N B4 Output HiSPi serial data, lane 2, differential N
SLVS2_P B5 Output HiSPi serial data, lane 2, differential P
V
AA
B7, B8 Power Analog power
EXTCLK C1 Input External input clock
V
DD
_SLVS C2 Power HiSPi power (May leave unconnected if parallel interface is used)
SLVS3_N C3 Output (Unsupported) HiSPi serial data, lane 3, differential N
SLVS3_P C4 Output (Unsupported) HiSPi serial data, lane 3, differential P
D
GND
C5, D4, D5, E5, F5, G5, H5 Power Digital GND
V
DD
A6, A7, B6, C6, D6 Power Digital power
A
GND
C7, C8 Power Analog GND
S
ADDR
D1 Input Two-Wire Serial address select
S
CLK
D2 Input Two-Wire Serial clock input
S
DATA
D3 I/O Two-Wire Serial data I/O
V
AA
_PIX D7, D8 Power Pixel power
LINE_VALID E1 Output Asserted when D
OUT
line data is valid
FRAME_VALID E2 Output Asserted when D
OUT
frame data is valid
PIXCLK E3 Output Pixel clock out. D
OUT
is valid on rising edge of this clock
FLASH E4 Output Control signal to drive external light sources
V
DD
_IO E6, F6, G6, H6, H7 Power I/O supply power
D
OUT
8 F1 Output Parallel pixel data output
D
OUT
9 F2 Output Parallel pixel data output
D
OUT
10 F3 Output Parallel pixel data output
D
OUT
11 F4 Output Parallel pixel data output (MSB)
TEST F7 Input Manufacturing test enable pin (connect to D
GND
)
D
OUT
4 G1 Output Parallel pixel data output
D
OUT
5 G2 Output Parallel pixel data output
D
OUT
6 G3 Output Parallel pixel data output
D
OUT
7 G4 Output Parallel pixel data output
TRIGGER G7 Input Exposure synchronization input (Connect to D
GND
if HiSPi interface
is used)
OE_BAR G8 Input Output enable (active LOW)
D
OUT
0 H1 Output Parallel pixel data output (LSB)
D
OUT
1 H2 Output Parallel pixel data output
D
OUT
2 H3 Output Parallel pixel data output
D
OUT
3 H4 Output Parallel pixel data output
RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to factory
default
Reserved E7, E8, F8 N/A Reserved (do not connect)
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Figure 7. 10 y 10 mm 48-pin iLCC Package, Parallel Output
42NC7
41NC8
40V
AA
9
39A
GND
10
38V
AA
_PIX11
37V
AA
_PIX12
36V
AA
13
35A
GND
14
34V
AA
15
33Reserved16
32Reserved17
V
DD
_IO 31Reserved18
D
OUT
7
D
OUT
8
D
OUT
9
D
OUT
10
D
OUT
11
V
DD
_IO
PIXCLK
V
DD
S
CLK
S
DATA
RESET_BAR
V
DD
6D
GND
19
NC 5EXTCLK20
NC 4V
DD
_PLL21
STANDBY 3D
OUT
622
OE_BAR 2D
OUT
523
S
ADDR
1D
OUT
424
TEST 48D
OUT
325
FLASH 47D
OUT
226
TRIGGER 46D
OUT
127
FRAME_VALID 45D
OUT
028
LINE_VALID 44D
GND
29
D
GND
43NC30
Table 4. PIN DESCRIPTIONS − 48-PIN ILCC PACKAGE, PARALLEL
Pin Number Name Type Description
1 D
OUT
4 Output Parallel pixel data output
2 D
OUT
5 Output Parallel pixel data output
3 D
OUT
6 Output Parallel pixel data output
4 V
DD
_PLL Power PLL power
5 EXTCLK Input External input clock
6 D
GND
Power Digital ground
7 D
OUT
7 Output Parallel pixel data output
8 D
OUT
8 Output Parallel pixel data output
9 D
OUT
9 Output Parallel pixel data output

AR0134CSSM25SUEAH3-GEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 1.2MP 1/3 CIS MONO2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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