WMS7202050P Datasheet WMS7202050P | P10-P12

WMS7202

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7.6. S

ERIAL DATA INTERFACE

The WMS7202 contains a four-wire SPI interface:

• SDO (Serial Data Output) Used for reading out the internal register contents and for daisy

chaining multiple devices.

• SDI (Serial Data Input) Used for clocking in commands and potentiometer settings.

• CS (Chip Select) This pin must be pulled LOW before starting to send a command and pulled

HIGH to signal the end of the command. This pin can be used to control multiple devices on

the bus.

• CLK (Clock) The SDI bits are shifted in on the rising edge of the clock and SDO data is

shifted out on the falling edge of the clock.

The key features of this interface include:

• Independently programmable Read & Write to all registers

• Direct parallel refresh of all Tap registers from corresponding internal NVMEM registers

• Increment and decrement instruction for each Tap register

• Nonvolatile storage of the present Tap register values into one of the four NVMEM registers

available to each channel

• Configurable output buffer amplifier to allow both the functions of a potentiometer and a

variable resistor

• Four 9-bit non-volatile registers store four preset wiper positions and the first one will be

recalled to set the wiper position during power up.

The serial interface uses an SPI compatible uniform 24-bit word format as shown below. This format is

used for all members of the WMS720x family. The data is sent MSB first.

TABLE 2 – 24-BIT DATA WORD FORMAT

MSB LSB

C3 C2 C1 C0 A3 A2 A1 A0 X X X X X X X D8 D7 D6 D5 D4 D3 D2 D1 D0

C3-C0 are the command bits that control the operation of the digital potentiometer according to the

command instructions shown in the Instruction Set in Table 5 in Section 7.7.

A1 and A0 are the address bits that determine which channel is activated, as shown in the table

below. For the WMS7202 only the first two codes are used.

WMS7202

Publication Release Date: January 2003

- 11 - Revision 1.1

TABLE 3 – A1 AND A0 ADDRESS BIT DECODE TABLE

[A1 A0] [0 0] [0 1]

[1 0] [1 1]

Channel 0 1 2 3

A3 and A2 are the address bits that decide which NVMEM memory to be accessed, as shown in the

table below.

TABLE 4 – A3 AND A2 ADDRESS BIT DECODE TABLE

[A3 A2] [0 0] [0 1] [1 0] [1 1]

NVMEM 0 1 2 3

D7-D0 are the data values to be loaded into the Tap Register to set the wiper position, while D8 is

used to set the output mode. D8 has to be loaded into the NVMEM0~3 first and then the “Load Tap

mode. D8=0 sets the output to Buffer Off mode while D8=1 sets to Buffer On mode.

FIGURE 5 – SPI COMMAND WAVEFORMS

CS is taken LOW

before command

starts

CS is taken HIGH

after command is

sent

R/B

Note:

• A multiple of 24 bits must always be sent or the

command will not be valid

• Bits marked ‘x’ are don’t care bits.

R/B goes LOW at completion of commands

2, 4, 5, 6 and 7 to allow NVMEM to program

for T

. For other commands, R/B stays

HIGH after command is sent.

SDO SDI must be valid on the rising edge of the clock

SDO is valid on the falling edge of the clock o

C2 C1 C0 A3 A2 A1 A0 x x x x x x x D8 D7 D6 D5 D4 D3 D2 D1 D0

2 3 4 5 6 7 8 9 1

SDI

WMS7202

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7.7. I

NSTRUCTION SET

TABLE 5 – INSTRUCTION SET

Inst

No.

Instruction Byte

C3 C2 C1 C0 A3 A2 A1

Data Byte 1

D15 D14 D13 D12 D11 D10 D9 D8

Data Byte 2

D7 D6 D5 D4 D3 D2 D1 D0

Operation

1 0 0 0 0 x x x x x x x x x x x x x x x x x x x x

No Operation (NOP). Do nothing

2 1 1 0 0 x x A1 A0 x x x x x x x x x x x x x x x x

Read Tap Register and output

selection MUX register

3 0 1 0 0 x x A1 A0 x x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0

Write to Tap Register with D7-D0

4 1 0 1 0 A3 A2 A1 A0 x x x x x x x x x x x x x x x x

Read NVMEM pointed to by A3-A0

5 0 0 1 0 A3 A2 A1 A0 x x x x x x x

D7 D6 D5 D4 D3 D2 D1 D0

Program NVMEM pointed to by

A3-A0 with D8-D0

6 1 0 1 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x

Load Tap Register and output

selection MUX register with the

contents of NVMEM pointed to by

A3-A0

7 0 0 1 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x

Program NVMEM pointed to by

A3-A0 with the contents of Tap

8 0 1 1 1 x x A1 A0 x x x x x x x x x x x x x x x x

Up: Increment setting of TR by one

tap

9 1 1 1 1 x x A1 A0 x x x x x x x x x x x x x x x x

Down: Decrement setting of TR by

one tap

10 1 0 0 0 x x x x x x x x x x x x x x x x x x x x

Sleep: Discontinue clock supply to

the logic and memories

11 0 0 0 1 x x x x x x x x x x x x x x x x x x x x

Wake Up: Clock supply to the logic

and memories

12 1 1 0 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x

Byte-erase NVMEM pointed to by

A3-A0

13 1 0 0 1 x x x x x x x x x x x x x x x x x x x x

Power On Reset: Software reset

the part to the power up state

Note: C3-C0 are the command op-code; A3, A2 are the NVMEM address; A1, A0 are the channel address.

7.8. B

ASIC OPERATION

This chapter describes the sequences of commands to send to the WMS7202 and how to use the

different features.

7.8.1 Sending a Command

1. Take the chip out of SLEEP mode.

2. Check that the write protect is set correctly if writing to NVMEM.

3. Check that R/B is HIGH before issuing command.

4. Pull the

CS pin LOW before sending data to the device.

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