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WMS7202050P

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
WMS7202
Publication Release Date: January 2003
- 19 - Revision 1.1
10. ELECTRICAL CHARACTERISTICS
TABLE 12 – ELECTRICAL CHARACTERISTICS
All Parameters apply across specified operating ranges unless noted (V
DD
: 2.7V~5.5V; Temp: –40°C~85°C)
Typical values: V
DD
=5V and T=25°C
PARAMETER SYMBOL MIN. TYP MAX. UNITS CONDITIONS
Rheostat Mode
Nominal Resistance R -20 +20 % T=25ºC, V
W
open
Different Non Linearity
DNL -1 0.3 +1 LSB
Integral Non Linearity
INL -1 0.5 +1 LSB
Rheostat Tempco
1
∆R
AB
/∆T
500
ppm/°
C
Wiper Resistance
2
R
W
50 100 Ω
V
DD
=5V,
I=V
DD
/R
Total
80 120 Ω
V
DD
=2.7V,
I=V
DD
/R
Total
Potentiometer Mode
Resolution
1
N 8 Bits
Different Non Linearity
2
DNL -1 +1 LSB
Integral Non Linearity
2
INL -1 +1 LSB
Potentiometer Tempco
1
∆V
w
/∆T
+20
ppm/°
C
Code = 80h
Full Scale Error V
FSE
-1 0 LSB Code = Full Scale
Zero Scale Error V
ZSE
0 1 LSB Code = Zero Scale
Resistor Terminal
Voltage Range
1
V
A
,V
B
,V
W
V
SS
V
DD
V
Terminal Capacitance
1
C
A
, C
B
30 pF
Wiper Capacitance
1
30 pF
Dynamic Characteristics
1
BW
10K
1.5 MHz V
DD
=5V, V
B
=V
SS
Code = Full Scale
Bandwidth –3dB BW
50K
300 KHz Code = 80h
BW
100K
200 KHz CL=30pf
Settling Time to 1 LSB T
S
80 100 uS V
DD
=5.5V=V
A
,
V
B
=V
SS
Analog Output (Buffer enabled)
Amp Output Current
2
I
OUT
3 mA V
O
=1/2 scale
Amp Output Resistance
2
Rout 1 10 Ω
Total Harmonic Distortion
1
THD 0.08 %
V
A
=2.5V, V
DD
=5V,
f=1kHz, V
IN
=1V
RMS
Digital Inputs/Outputs
Input High Voltage V
IH
0.7V
DD
V
Input Low Voltage V
IL
0.3V
DD
V
Output Low Voltage V
OL
0.4 V I
OL
=2mA
Input Leakage Current I
LI
-1 +1 uA
CS =V
DD
,Vin=Vss
WMS7202
- 20 -
~ V
DD
Output Leakage Current I
Lo
-1 +1 uA
CS =V
DD
,Vin=V
SS
~ V
DD
Input Capacitance
1
C
IN
25 pF
V
DD
=5V, fc = 1Mhz
Code = 80h
Output Capacitance
1
C
OUT
25 pF
V
DD
=5V, fc = 1Mhz
Code = 80h
Power Requirements
Operating Voltage
1
V
DD
2.7 5.5 V
Operating Current I
DDR
1 1.8 mA
All ops except
NVMEM program
Operating Current I
DDW
1 2 mA
During Non-
volatile memory
program
I
SA
0.5 1 mA
Buffer is active, ,
no load
Standby Current
I
SB
2
0.1 1 uA
Buffer is inactive,
Power Down, No
load
Power Supply Rejection Ratio PSRR 1 LSB/V
V
DD
=5V±10%,
Code=80h
Note: 1. Not subject to production test; 2. Only on Final Test; 3. V
DD
= +2.7V to 5.5V, V
SS
= 0V, T = 25ºC, unless otherwise
noted.
WMS7202
Publication Release Date: January 2003
- 21 - Revision 1.1
10.1 T
EST CIRCUITS
FIGURE 7 – TEST CIRCUITS
Potentiometer divider nonlinearit
y
error
test circuit
(
INL, DNL
)
*Assume infinite in
p
ut im
p
edance
V
+
V
MS
*
V
+
= V
DD
1LSB= V
+
/255
WMS7202
V
A
V
B
V
W
Resistor
p
osition nonlinearit
y
error test
circuit (Rheostat Operation: R-INL, R-DNL)
*Assume infinite in
p
ut im
p
edance
No Connection
V
MS
*
WMS7202
W
V
A
V
B
V
W
I
W
WMS7202
Wi
p
er resistance test circuit
*Assume infinite in
p
ut im
p
edance
V
MS
*
WMS7202
V
A
V
B
V
W
I
W
I
W
= V
DD
/R
Total
R
W
= V
MS
/I
W
Power supply sensitivity test circuit (PSS, PSRR)
*Assume infinite in
p
ut im
p
edance
V
+
V
+
= V
DD
±
10%
V
A
V
B
V
W
V
MS
*
PSRR
(
dB
)
= 20LOG
(
)
∆
V
MS
∆
V
DD
PSS
(
%/%
)
=
∆
V
MS
∆
V
DD
WMS7202
V
A
V
B
V
W
V
IN
~
+5V
2.5V DC
Offset
V
OUT
Ca
p
acitance test circuit
V
A
V
B
WMS7202
V
W
V
IN
~
+5V
2.5V DC
V
OUT
OFFSET
GND
Gain vs. fre
q
uenc
y
test circuit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

WMS7202050P

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IC DGTL POT 50KOHM 256TAP 14DIP
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