LT3782A
7
3782afc
For more information www.linear.com/LT3782A
GBIAS2
R2
50k
A18
ONE SHOT
A19
A2
60mV
CH1
CL1
PWM1
A3
R3
3782A BD
C2
2nF
C
IN
20µF
R
FREQ
R
S1
M1
R8
R6
C
OUT
100µF
V
OUT
V
IN
+
C3
2µF
R
S2
V
CC
RUN
SYNC
DELAY
DELAY
DELAY
SLOPE
R
SET
DCL
R
SET
GND
C1
2000pF
R5
2k
C7
10nF
GBIAS2
GBIAS
GBIAS1
BGATE1
BGATE1
BGATE1
SGATE1
BGATE2
V
EE1
V
EE2
V
REF
SENSE1
+
SENSE1
SENSE2
+
SENSE2
FB
M2
GBIAS1
R7
10Ω
C4
2nF
R9
10Ω
R
F2
R
F1
R1
50k
L1
15µH
D1
D2
L2
15µH
+
+
6
5
17
27
10
7
V
C
15
SS
14
11
4
SGATE1
SGATE2
1
2
22
21
28
23
8
9
24
20
13
12
19
16
REGULATOR
SLOPE
COMP
OSC
LOGIC
QCK
QD
CH1
SET
RS
7V
+
+
0.5V
+
+
2.44V
+
+
2.5V
+
V
CC
– 2.5V
A6
A11
A12
A5
A7
A8
LOW POWER
SHUTDOWN
V
GBIAS
= V
CC
– 1V AND CLAMPED AT 11V
NOTE:
PACKAGE BOTTOM METAL PLATE (PIN 29)
IS FUSED TO CHIP DIE AGND
A20
A1A4
A17A15
A13
C5
20pF
+
ONE SHOT
BLANKING
A14
A9
+
+
SLOPE COMP
60mV
A10
R4
BLANKING
+
+
+
CH2
RS
SLOPE COMP
4V
BGATE2
+
2.5V
+
+
+
GM
D6
D7
D4
I1
10µA
CH2
CL2
PWM2
A16
SET
block DiagraM
LT3782A
8
3782afc
For more information www.linear.com/LT3782A
Operation
The LT3782A is a two phase constant frequency current
mode boost controller. Switching frequency can be pro-
grammed up to 500kHz. During normal switching cycles,
the two channels are controlled by internal flip-flops and
are 180 degrees out-of-phase.
Referring to the Block Diagram, the LT3782A’s basic func-
tions include a transconductance amplifier (g
m
) to regulate
the output voltage and to control the current mode PWM
current loop. It also includes the necessary logic and flip-
flop to control the PWM switching cycles, two high speed
gate drivers to drive high power N-channel MOSFETs, and
2-phase control signals to drive external gate drivers for
optional synchronous operation.
In normal operation, each switching cycle starts with a
switch turn-on. The inductor current of each channel is
sampled through the current sense resistor and amplified
then compared to the error amplifier output V
C
to turn
the switch off. The phase delay of the second channel is
controlled by the divide-by-two D flip-flop and is exactly
180 degrees out-of-phase of the first channel. With a re-
sistor divider connected to the FB pin, the output voltage
is programmed to the desired value. The 10V gate drivers
are sufficient to drive most high power N-channel MOSFET
in many industrial applications.
Additional important features include shutdown, cur-
rent limit, soft-start, synchronization and programmable
maximum duty cycle. Additional slope compensation can
be added also.
Output Voltage Programming
With a 2.44V feedback reference voltage V
REF
, the output
V
OUT
is programmed by a resistor divider as shown in
the Block Diagram.
V
OUT
= 2.44 1+
R
F1
R
F2
Soft-Start and Shutdown
During soft-start, the voltage on the SS pin (V
SS
) controls
the output voltage. The output voltage thus ramps up fol-
lowing V
SS
. The effective range of V
SS
is from 0V to 2.44V.
The typical time for the output to reach the programmed
level is:
t =
C 2.44V
10µA
C is the capacitor connected from the SS pin to GND.
Undervoltage Lockout and Shutdown
Only when V
RUN
is higher than 2.45V V
GBIAS
will be active
and the switching enabled. The LT3782A goes into low
current shutdown when V
RUN
is below 0.3V. A resistor
divider can be used on RUN pin to set the desired V
CC
undervoltage lockout voltage. 80mV of hysteresis is built
in on RUN pin thresholds.
Oscillation Frequency Setting and Synchronization
The switching frequency of LT3782A can be set up to
500kHz by a resistor R
FREQ
from pin R
SET
to ground.
For f
SET
= 250kHz, R
FREQ
= 80k
Once the switching frequency f
SET
is chosen, R
FREQ
can be
found from the Switching Frequency vs R
FREQ
graph found
under the Typical Performance Characteristics section.
Note that because of the 2-phase operation, the internal
oscillator is running at twice the switching frequency. To
synchronize the LT3782A to the system frequency f
SYSTEM
,
the synchronizing frequency f
SYNC
should be two times
f
SYSTEM
, and the LT3782A switching frequency f
SET
should
be set below 80% of f
SYSTEM
.
f
SYNC
= 2f
SYSTEM
and f
SET
< (f
SYSTEM
• 0.8)
For example, to synchronize the LT3782A to 200kHz sys-
tem frequency f
SYSTEM
, f
SYNC
needs to be set at 400kHz
and f
SET
needs to be set at 160kHz. From the Switching
Frequency vs R
FREQ
graph found under the Typical Per-
formance Characteristics section, R
FREQ
= 130k.
applicaTions inForMaTion
LT3782A
9
3782afc
For more information www.linear.com/LT3782A
With a 200ns one-shot timer on chip, the LT3782A provides
flexibility on the external sync pulse width. The sync pulse
threshold is about 1.2V (Figure 1). This pin can be floated
when the sync function is not used.
Current Limit
Current limit is set by the 63mV threshold across SEN1P,
SEN1N for channel one and SEN2P, SEN2N for channel
two. By connecting an external resistor R
S
(see Block
Diagram), the current limit is set for 63mV/R
S
. R
S
should
be placed very close to the power switch with very short
traces. A low pass R
C
filter is needed across R
S
to filter out
the switching spikes. Good Kelvin sensing is required for
accurate current limit. The input bypass capacitor ground
should be at the same ground point of the current sense
resistor to minimize the ground current path.
Synchronous Rectifier Switches
For high output voltage applications, the power loss of the
catch diodes are relatively small because of high duty cycle.
If diodes power loss or heat is a concern, the LT3782A
provides PWM signals through SGATE1 and SGATE2 pins
to drive external MOSFET drivers for synchronous recti
-
fier operation.
Note that SGATE drives the top switch and
BGATE drives the bottom switch. To avoid cross conduction
between top and bottom switches, the BGATE turn-on is
delayed 100ns (when DELAY pin is tied to R
SET
pin) from
SGATE turn-off (see Figure 2). If a longer delay is needed
to compensate for the propagation delay of external gate
driver, a resistor divider can be used from R
SET
to ground to
program V
DELAY
for the longer delay needed. For example,
for a switching frequency of 250kHz and delay of 150ns,
then R
FREQ1
+ R
FREQ2
should be 80k and V
DELAY
should
be 1V, with V
RSET
= 2.3V then R
FREQ1
= 47.5k and R
FREQ2
= 32.5k (see Figure 3).
Duty Cycle Limit
When DCL pin is shorted to R
SET
pin and switching fre-
quency is less than 250kHz (R
FREQ
> 80k), the maximum
duty cycle of LT3782A will be at least 90%. The maximum
duty cycle can be clamped to 50% by grounding the DCL
pin or to 75% by forcing the V
DCL
voltage to 1.2V with a
resistor divider from R
SET
pin to ground. The typical DCL
pin input current is 0.1µA.
Figure 1. Synchronizing with External Clock Figure 2. Delay Timing
5V TO 20V
VN2222
PULSE WIDTH > 200ns
5k
SYNC
3782A F01
LT3782A
3782A F02
DELAY
BGATE1
SGATE1
SET
applicaTions inForMaTion
Figure 3. Increase Delay Time
R
SET
DELAY
LT3782A
R
FREQ2
32.5k
R
FREQ1
47.5k
3782A F03

LT3782AEFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-PhBoost DC/DC Cntr
Lifecycle:
New from this manufacturer.
Delivery:
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