CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 13 of 25
Note:
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
TAP Controller State Diagram
[9]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
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CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 14 of 25
TAP Controller Block Diagram
0
012..
29
3031
Boundary Scan Register
Identification Register
012..
.
.
106
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
TAP Electrical Characteristics Over the Operating Range
[15, 18, 10]
Parameter Description Test Conditions Min. Max. Unit
V
OH1
Output HIGH Voltage I
OH
=2.0 mA 1.4 V
V
OH2
Output HIGH Voltage I
OH
=100 µA1.6 V
V
OL1
Output LOW Voltage I
OL
= 2.0 mA 0.4 V
V
OL2
Output LOW Voltage I
OL
= 100 µA0.2V
V
IH
Input HIGH Voltage 0.65V
DD
V
DD
+ 0.3 V
V
IL
Input LOW Voltage –0.3 0.35V
DD
V
I
X
Input and OutputLoad Current GND V
I
V
DD
55µA
Note:
10.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
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CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 15 of 25
TAP AC Switching Characteristics Over the Operating Range
[11, 12]
Parameter Description Min. Max. Unit
t
TCYC
TCK Clock Cycle Time 50 ns
t
TF
TCK Clock Frequency 20 MHz
t
TH
TCK Clock HIGH 20 ns
t
TL
TCK Clock LOW 20 ns
Set-up Times
t
TMSS
TMS Set-up to TCK Clock Rise 5 ns
t
TDIS
TDI Set-up to TCK Clock Rise 5 ns
t
CS
Capture Set-up to TCK Rise 5 ns
Hold Times
t
TMSH
TMS Hold after TCK Clock Rise 5 ns
t
TDIH
TDI Hold after Clock Rise 5 ns
t
CH
Capture Hold after Clock Rise 5 ns
Output Times
t
TDOV
TCK Clock LOW to TDO Valid 10 ns
t
TDOX
TCK Clock LOW to TDO Invalid 0 ns
TAP Timing and Test Conditions
[12]
Notes:
11. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
12.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9V
50
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
t
TCYC
t
TMSH
t
TL
t
TH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
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CY7C1425AV18-250BZXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 36M PARALLEL 165FBGA
Lifecycle:
New from this manufacturer.
Delivery:
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