CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 18 of 25
Power-Up Sequence in QDR-II SRAM
[13, 14]
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
• Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
—Apply V
DD
before V
DDQ
—Apply V
DDQ
before V
REF
or at the same time as V
REF
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock.
DLL Constraints
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
t
KC Var
.
• The DLL will function at frequencies down to 80MHz.
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
.
Notes:
13.It is recommended that the DOFF
pin be pulled HIGH via a pull up resistor of 1 Kohm.
14.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Power-up Waveforms
> 1024 Stable clock
Start Normal
Operation
DOFF
Stable (< +/- 0.1V DC per 50ns )
Fix High (or tied to V
DDQ
)
K
K
DDQ
DD
V
V
/
DDQ
DD
V
V
/
Clock Start
(Clock Starts after Stable)
DDQ
DD
V
V
/
~
~
Unstable Clock
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