MR45V100AMAZAATL

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

FEDR45V100A-01

MR45V100A

13/21

RECOMMENDED OPERATING CONDITIONS

POWER SUPPLY VOLTAGE

Parameter Symbol

Min. Typ. Max. Unit

Power Supply Voltage

V

CC

1.8 3.3 3.6 V

Ground Voltage

V

SS

0 0 0 V

DC INPUT VOLTAGE

Parameter Symbol

Min. Max. Unit

Input High Voltage

V

IH

V

CC

x 0.7 V

CC

+0.3

V

Input Low Voltage

V

IL

–0.3

V

CC

x 0.3

V

OVERSHOOT/UNDERSHOOT TOLERANCE (Input signal)

Parameter Symbol

Pulse Width Peak

“H” input

V

IH OVERSHOOT

≤ 20ns

V

CC

+1.0V

“L” input

V

IL UNDERSHOOT

≤ 20ns

– 1.0V

FEDR45V100A-01

MR45V100A

14/21

DC CHARACTERISTICS

DC INPUT/OUTPUT CHARACTERISTICS

Parameter Symbol Condition

Min. Max. Unit Note

Output High Voltage

V

OH

I

OH

=–2mA

V

CC

×0.85

― V

Output Low Voltage

V

OL

I

OL

=2mA

―

V

CC

×0.15

V

Input Leakage Current

I

LI

― –10 10 µA

Output Leakage

Current

I

LO

― –10 10 µA

POWER SUPPLY CURRENT

V

CC

=Max.to Min, Ta=Topr

Parameter Symbol Condition

Min. Typ. Max. Unit Note

Power Supply Current

(Standby)

I

CCS

CS#= V

CC

,

Other input terminals:

V

IN

=0V or V

CC

― 10 50 µA 1

Power Supply Current

(Sleep)

I

ZZ

CS#=V

CC,

Other input terminals :

V

IN

=0V or V

CC

― 0.1 2 µA 1

Power Supply Current

(Operating)

I

CCA

SCK=40MHz,

I

OUT

=0mA

― 3 4.5 mA 1

Note: 1. Average electric current.

FEDR45V100A-01

MR45V100A

15/21

AC CHARACTERISTICS

SPI mode AC characteristics

V

CC

=Max. to Min., Ta=Topr.

Parameter Symbol

Read Cycle Except for READ

Unit Note

Min. Max. Min. Max.

Clock frequency

f

C

D.C. 34 D.C. 40 MHz

CS# setup time

t

SLCH

10 ― 10 ― ns

CS# De-select time

t

SHSL

10 ― 10 ― ns

CS# De-select time

(SLEEP)

t

SHSL_SL

300 ― 300 ― ns

CS# active hold time

t

CHSH

10 ― 10 ― ns

SCK High time

t

CH

13 ― 11 ― ns 1

SCK Low time

t

CL

13 ― 11 ― ns 1

Data Setup time

t

DVCH

5 ― 5 ― ns

Data Hold time

t

CHDX

5 ― 5 ― ns

SCK Low Hold time

after HOLD# inactive

t

HHCH

10 ― 10 ― ns

SCK Low Hold time

after HOLD# active

t

HLCH

10 ― 10 ― ns

SCK High Setup time

before HOLD# active

t

CHHL

10 ― 10 ― ns

SCK High Setup time

before HOLD#

inactive

t

CHHH

10 ― 10 ― ns

Output disable time

t

SHQZ

― 12 ― 12 ns 2

SCK Low to Output

Valid time

t

CLQV

― 12 ― 9 ns

V

CC

≧

2.7V

― 13 ― 10 ns

V

CC

<2.7V

Output Hold time

t

CLQX

0 ― 0 ― ns

Input rise time

t

RI

― 50 ― 50 ns 2

Inputt fall time

t

FI

― 50 ― 50 ns 2

HOLD# High to

Output Low

impedance time

t

HHQX

― 20 ― 20 ns 2

HOLD# High to

Output High

impedance time

t

HLQZ

― 20 ― 20 ns 2

Recovery time from

SLEEP mode

t

REC

― 100 ― 100 µs

Note: 1. t

CH

＋t

CL

≧

1/f

C

2. sample value

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

MR45V100AMAZAATL

Mfr. #:

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Description:

F-RAM FeRAM/1Mbit 128Kbx8 8pin SOP 34MHz

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MR45V100AMAZAATL