FEDR45V100A-01
MR45V100A
7/21
READ (Read from Memory Array)
READ command can be valid when CS# goes “L”, then the op-code and 24bit-addresses are inputted to serial
input ”SI”. The inputted addresses are loaded to internal register, then the data from corresponded address is
outputted at serial-output “SO”. If CS# will keep “L”, the internal address will be increased automatically after
8 clocks and will output the data from new-address. When it reaches the most significant address, the address
counter rolls over to starting address, and reading cycle can be continued infinitely. To finish read cycle, make
the CS# “H” during LSB output clock.
FSTRD (Fast Read from Memory Array)
FSTRD command can be valid when CS# goes “L”, then the op-code and 24bit-addresses are inputted to serial
input ”SI”. After 8bits for dummy byte, the data from corresponded address is outputted at serial-output “SO”.
If CS# will keep “L”, the internal address will be increased automatically after 8 clocks and will output the data
from new-address. When it reaches the most significant address, the address counter rolls over to starting address,
and reading cycle can be continued infinitely. To finish read cycle, make the CS# “H” during LSB output
clock.
CS
SCK
SI
0
SO
High-Z
1 2 3 4 5 6 7 8 9 15 16 28 29 30 31
A2 A1 A0
23 22 16 3 2 1 0
A3 A16XX
24bit Address (An)
15
A15
CS
SCK
SI
32
SO
33 34 35 36 37 38 39 40 41 42 43 46 47 m
Data Out (An)
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Data Out (An+1)
Q0
44 45
Note : WP# = fixed ”H”
14
17
X
m-1
Q1
Q2
m-2
CS
SCK
SI
SO
High-Z
CS
SCK
SI
32
SO
33 34 35 36 37 38 39 40 41 42 43 46 47 m
Dumm
B
te
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Data Out
An
Q0
44 45
Note : WP# = fixed ”H”
Q1
0 1 2 3 4 5 6 7 8 9 15 16 28 29 30 31
A2 A1 A0
23 22 16 3 2 1 0
A3 A16XX
24bit Address (An)
15
A15
14
17
X
m-1
