FEDR45V100A-01
MR45V100A
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OPERATION-CODE
Operation codes are listed in the table below. If the device receives invalid operation code, the device will be
deselected.
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
FSTRD Fast Read from Memory Array 0000 1011
RDID Read device ID 1001 1111
SLEEP Enter Sleep Mode 1011 1001
FEDR45V100A-01
MR45V100A
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COMMANDS
WREN (Write Enable)
It is necessary to set Write Enable LatchWELbit before write-operation (WRITE and WRSR).
WREN command sets WEL bit.
WRDI (Write Disable)
WRDI command resets WEL bit.
CS
#
SC
K
SI
WP
#
Fixed “H”
0 1 2 3 4 5 6 7
SO
High-Z
CS
#
SC
K
SI
WP
#
Fixed “H”
0 1 2 3 4 5 6 7
SO
High-Z
FEDR45V100A-01
MR45V100A
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RDSR (READ Status Register)
The RDSR command allows reading data of status register. The Status Register can be read anytime and any
number of times.
WRSR (WRITE Status Register
WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable
LatchWELbit by WREN command before executing WRSR. WRSR command cannot write RFU(b6,b5,b4),
WEL(b1), WIP(b0) of Status Resistor..
CS
#
SC
K
SI
WP
#
Fixed “H”
0
SO
High-Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SRWD BP1 BP0 WEL WIP SRWD000
765432 1 07
CS
#
SC
K
SI
0
SO
High-Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BP0 X X
76543 2 1 0
BP1 XXXSRWD
Note:
WP#=Fixed ”H”

MR45V100AMAZAATL

Mfr. #:
Manufacturer:
Description:
F-RAM FeRAM/1Mbit 128Kbx8 8pin SOP 34MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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