19
LTC3738
3738f
V
CC
Decoupling
The V
CC
pin supplies power not only to the internal circuits
of the controller but also to the top and bottom gate
drivers and therefore must be bypassed very carefully to
ground with a ceramic capacitor, type X7R or X5R (de-
pending upon the operating temperature environment) of
at least 1
µ
F imme
diately next to the IC
and preferably an
additional 10µF placed very close to the IC due to the
extremely high instantaneous currents involved. The total
capacitance, taking into account the voltage coefficient of
ceramic capacitors, should be 100 times as large as the
total combined gate charge capacitance of ALL of the
MOSFETs being driven. Good bypassing close to the IC is
necessary to supply the high transient currents required
by the MOSFET gate drivers while keeping the 5V supply
quiet enough so as not to disturb the very small-signal
high bandwidth of the current comparators.
Topside MOSFET Driver Supply (C
B
, D
B
)
External bootstrap capacitors, C
B
, connected to the BOOST
pins, supply the gate drive voltages for the topside
MOSFETs. Capacitor C
B
in the Functional Diagram is
charged though diode D
B
from V
CC
when the SW pin is
low. When one of the topside MOSFETs turns on, the
driver places the C
B
voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
V
IN
and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply (V
BOOST
=
V
CC
+ V
IN
). The value of the boost capacitor C
B
needs to be
30 to 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of D
B
must be
greater than V
IN(MAX).
Differential Amplifier
The IC has a true remote voltage sense capability. The
sensing connections should be returned from the load,
back to the differential amplifier’s inputs through a
common, tightly coupled pair of PC traces. The differen-
tial amplifier rejects common mode signals capacitively
or inductively radiated into the feedback PC traces as well
as ground loop disturbances. The differential amplifier
output signal is divided down through the VID DAC and
is compared with the internal, precision 0.6V voltage
reference by the error amplifier.
The amplifier has a 0 to V
CC
common mode input range
and an output swing range of 0 to V
CC
– 1.2V. The output
uses an NPN emitter follower with 160k feedback
resistance.
Output Voltage
Selection of the VRM9 or VRM10 VID table is through the
VID5 pin. Tying VID5 to V
CC
will select the VRM9 VID table.
If the VRM9 VID table is selected (Table 1), output voltage
in 25mV increments is produced from 1.1V to 1.85V.
There is a built-in –12.5mV DC offset for the output
voltage.
If the VRM10 VID table is selected (Table 2), output voltage
in 12.5mV increments is produced from 0.8375V to 1.6V.
There is a built-in –25mV DC offset for output voltage.
Active Voltage Position Control
The LTC3738 senses inductor current information through
monitoring voltage drops on the sense resistor R
SENSE
of
all three channels. The voltage drops are added together
and applied as V
PRE-AVP
between the AVP and IN
+
pins,
which are connected through resistor R
PRE-AVP
. Then
V
PRE-AVP
is scaled through R
AVP
and added to output
voltage as the compensation for the load voltage drop. In
summary, the load slope is:
R
R
R
VA
SENSE
AVP
PRE AVP
•/
The recommended value for R
AVP
is 90 to 100.
APPLICATIO S I FOR ATIO
WUUU
20
LTC3738
3738f
Table 1. VRM9 VID Table
V
CC(CORE)
VID4 VID3 VID2 VID1 VID0 (V
DC
)
1 1 1 1 1 Output Off
1 1 1 1 0 1.100
1 1 1 0 1 1.125
1 1 1 0 0 1.150
1 1 0 1 1 1.175
1 1 0 1 0 1.200
1 1 0 0 1 1.225
1 1 0 0 0 1.250
1 0 1 1 1 1.275
1 0 1 1 0 1.300
1 0 1 0 1 1.325
1 0 1 0 0 1.350
1 0 0 1 1 1.375
1 0 0 1 0 1.400
1 0 0 0 1 1.425
1 0 0 0 0 1.450
0 1 1 1 1 1.475
0 1 1 1 0 1.500
0 1 1 0 1 1.525
0 1 1 0 0 1.550
0 1 0 1 1 1.575
0 1 0 1 0 1.600
0 1 0 0 1 1.625
0 1 0 0 0 1.650
0 0 1 1 1 1.675
0 0 1 1 0 1.700
0 0 1 0 1 1.725
0 0 1 0 0 1.750
0 0 0 1 1 1.775
0 0 0 1 0 1.800
0 0 0 0 1 1.825
0 0 0 0 0 1.850
PROCESSOR PINS (0 = L0W, 1 = HIGH)
APPLICATIO S I FOR ATIO
WUUU
Thermal Control
When external thermal detection is enabled, the TSNS pin
serves as the input to an accurate comparator which is
referenced to V
CC
/3 and has a hysteresis of V
CC
/24.
VR_HOTB is pulled low when the voltage at TSNS is less
than V
CC
/3. In this case, the input of TSNS is an analog
signal. If necessary, lowpass filter the signal before feed-
ing it into the pin to avoid a false thermal trip.
When VR_HOTB is reported, the operation of LTC3738 will
not be affected, although there is another thermal sensor
inside the IC for self protection. When the temperature of
the IC is around 140°C, the LTC3738 will shut down and
not start-up again until this overtemperature situation has
been removed. This self shutdown feature is not tested but
is guaranteed by design.
ON/OFF Control
The OUTEN pin provides simple ON/OFF control for the
LTC3738. Driving the OUTEN pin above 0.8V permits the
controller to start operating. Pulling OUTEN below 0.4V
puts the LTC3738 into low current shutdown (I
Q
50µA).
Soft-Start Function
The SS pin provides two functions: 1) soft-start and 2) a
defeatable short-circuit latch off timer. Soft-start reduces
the input power sources’ surge currents by gradually
increasing the controller’s current limit (proportional to an
internal buffered and clamped V
ITH
). The latchoff timer
prevents very short, extreme load transients from tripping
the overcurrent latch. A small pull-up current (>5µA)
supplied to the SS pin will prevent the overcurrent latch
from operating. The following explanation describes how
this function operates.
An internal 1.5µA current source charges up the C
SS
capacitor. As the voltage on SS increases from 0V to 2.4V,
21
LTC3738
3738f
Table 2. VRM10 VID Table
V
OUT
V
OUT
VID4 VID3 VID2 VID1 VID0 VID5
(V)
VID4 VID3 VID2 VID1 VID0 VID5
(V)
0 1 0 1 0 0 0.8375 1 1 0 1 0 0 1.2125
0 1 0 0 1 1 0.8500 1 1 0 0 1 1 1.2250
0 1 0 0 1 0 0.8625 1 1 0 0 1 0 1.2375
0 1 0 0 0 1 0.8750 1 1 0 0 0 1 1.2500
0 1 0 0 0 0 0.8875 1 1 0 0 0 0 1.2625
0 0 1 1 1 1 0.9000 1 0 1 1 1 1 1.2750
0 0 1 1 1 0 0.9125 1 0 1 1 1 0 1.2875
0 0 1 1 0 1 0.9250 1 0 1 1 0 1 1.3000
0 0 1 1 0 0 0.9375 1 0 1 1 0 0 1.3125
0 0 1 0 1 1 0.9500 1 0 1 0 1 1 1.3250
0 0 1 0 1 0 0.9625 1 0 1 0 1 0 1.3375
0 0 1 0 0 1 0.9750 1 0 1 0 0 1 1.3500
0 0 1 0 0 0 0.9875 1 0 1 0 0 0 1.3625
0 0 0 1 1 1 1.0000 1 0 0 1 1 1 1.3750
0 0 0 1 1 0 1.0125 1 0 0 1 1 0 1.3875
0 0 0 1 0 1 1.0250 1 0 0 1 0 1 1.4000
0 0 0 1 0 0 1.0375 1 0 0 1 0 0 1.4125
0 0 0 0 1 1 1.0500 1 0 0 0 1 1 1.4250
0 0 0 0 1 0 1.0625 1 0 0 0 1 0 1.4375
0 0 0 0 0 1 1.0750 1 0 0 0 0 1 1.4500
0 0 0 0 0 0 1.0875 1 0 0 0 0 0 1.4625
1 1 1 1 1 1 Off* 0 1 1 1 1 1 1.4750
1 1 1 1 1 0 Off* 0 1 1 1 1 0 1.4875
1 1 1 1 0 1 1.1000 0 1 1 1 0 1 1.5000
1 1 1 1 0 0 1.1125 0 1 1 1 0 0 1.5125
1 1 1 0 1 1 1.1250 0 1 1 0 1 1 1.5250
1 1 1 0 1 0 1.1375 0 1 1 0 1 0 1.5375
1 1 1 0 0 1 1.1500 0 1 1 0 0 1 1.5500
1 1 1 0 0 0 1.1625 0 1 1 0 0 0 1.5625
1 1 0 1 1 1 1.1750 0 1 0 1 1 1 1.5750
1 1 0 1 1 0 1.1875 0 1 0 1 1 0 1.5875
1 1 0 1 0 1 1.2000 0 1 0 1 0 1 1.6000
*Output disabled—same as deasserting the Output Enable input
PROCESSOR PINS (0 = LOW, 1 = HIGH) PROCESSOR PINS (0 = LOW, 1 = HIGH)
the internal current limit is increased from 0V/R
SENSE
to
75mV/R
SENSE
. The output current limit ramps up slowly,
taking 1.6s/µF to reach full current. The output current
thus ramps up slowly, eliminating the starting surge
current required from the input power supply.
t
VV
A
CsFC
IRAMP SS SS
=
µ
()
24 0
15
16
.–
.
./
The SS pin has an internal 6V zener clamp (see the
Functional Diagram).
Fault Conditions: Overcurrent Latchoff
The SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
SS capacitor is used initially to limit the inrush current of
all three output stages. After the controllers have been

LTC3738CUHF#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3-Phase VRM10/VRM9 Synch. Controller
Lifecycle:
New from this manufacturer.
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