LTC3738CUHF#PBF Datasheet LTC3738CUHF#TRPBF, LTC3738CUHF#PBF | P22-P24

LTC3738

3738f

given adequate time to charge up the output capacitor and

provide full load current, the SS capacitor is used for a

short-circuit timer. If the output voltage falls to less than

62.5% of its nominal value, the SS capacitor begins

discharging on the assumption that the output is in an

overcurrent condition. If the condition lasts for a long

enough period, as determined by the size of the SS

capacitor, the controller will be shut down until the RUN

pin voltage is recycled. If the overload occurs during start-

up, the time can be approximated by:

LO1

>> (C

• 0.6V)/(1.5µA) = 4 • 10

)

If the overload occurs after start-up, the voltage on the SS

capacitor will continue charging and will provide addi-

tional time before latching off:

LO2

>> (C

• 3V)/(1.5µA) = 2 • 10

)

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor to the SS pin from V

shown in Figure 6. When V

is 5V, a 200k resistance will

prevent the discharge of the SS capacitor during an

overcurrent condition but also shortens the soft-start

period, so a larger SS capacitor value will be required.

Why should you defeat overcurrent latchoff? During the

prototyping stage of a design, there may be a problem with

noise pick-up or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

foldback current limiting still remains active, thereby

protecting the power supply system from failure. A deci-

sion can be made after the design is complete whether to

rely solely on foldback current limiting or to enable the

latchoff feature by removing the pull-up resistor.

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The value of the soft-start capacitor C

may need to be

scaled with output current, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

> (C

OUT

)(V

OUT

) (10

–4

) (R

SENSE

)

The minimum recommended soft-start capacitor of

= 0.1µF will be sufficient for most applications.

Current Foldback

In certain applications, it may be desirable to defeat the

internal current foldback function. A negative impedance

is experienced when powering a switching regulator.

That

is, the input current is higher at a lower V

and

decreases as V

is increased. Current foldback is de-

signed to accommodate a normal, resistive load having

increasing current draw with increasing voltage. The EAIN

pin should be artificially held 62.5% above its nominal

operating level of 0.6V, or 0.375V in order to prevent the

IC from “folding back” the peak current level. A suggested

circuit is shown in Figure 7.

The emitter of Q1 will hold up the EAIN pin to a voltage in

the absence of V

OUT

that will prevent the internal sensing

circuitry from reducing the peak output current. Remov-

ing the function in this manner eliminates the external

MOSFET’s protective feature under short-circuit condi-

tions. This technique will also prevent the short-circuit

latchoff function from turning off the part during a short-

circuit event and the output current will only be limited to

N • 75mV/R

SENSE

SS PIN

3738 F06

Figure 6. Defeating Overcurrent Latchoff

Figure 7. Foldback Current Elimination

3738 F07

CALCULATE FOR

0.375V TO 0.55V

EAIN

LTC3738

3738f

Undervoltage Reset

In the event that the input power source to the IC (V

)

drops below 4V, the SS capacitor will be discharged to

ground and the controller will be shut down. When V

rises above 4V, the SS capacitor will be allowed to re-

charge and initiate another soft-start turn-on attempt. This

may be useful in applications that switch between two

supplies that are not diode connected, but note that this

cannot make up for the resultant interruption of the

regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This

allows the top MOSFET of output stage 1’s turn-on to be

locked to the rising edge of an external source. The

frequency range of the voltage controlled oscillator is

±50% around the center frequency f

. A voltage applied to

the PLLFLTR pin of 1.2V corresponds to a frequency of

approximately 350kHz. The nominal operating frequency

range of the IC is 210kHz to 530kHz.

The phase detector used is an edge sensitive digital type

that provides zero degrees phase shift between the

external and internal oscillators. This type of phase

detector will not lock the internal oscillator to harmonics

of the input frequency. The PLL hold-in range, ∆f

, is

equal to the capture range, ∆f

∆f

= ∆f

= ±0.5 f

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter components on the PLLFLTR pin. A simplified block

diagram is shown in Figure 8.

If the external frequency (f

PLLIN

) is greater than the oscil-

lator frequency, f

OSC

, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f

OSC

, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same, but exhibit a phase difference, the

current sources turn on for an amount of time correspond-

ing to the phase difference. Thus, the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point, the phase comparator output is

open and the filter capacitor C

holds the voltage. The IC

FCB/SYNC pin must be driven from a low impedance

source such as a logic gate located close to the pin. When

using multiple ICs for a phase-locked system, the PLLFLTR

pin of the master oscillator should be biased at a voltage

that will guarantee the slave oscillator(s) ability to lock

onto the master’s frequency. A voltage of 1.7V or below

applied to the master oscillator’s PLLFLTR pin is recom-

mended in order to meet this requirement. The resultant

operating frequency will be approximately 500kHz for

1.7V.

The loop filter components (C

, R

) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C

and R

determine how fast the loop

acquires lock. Typically R

=10k and C

ranges from

0.01µF to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration

that the IC is capable of turning on the top MOSFET. It is

determined by internal timing delays and the gate charge

of the top MOSFET. Low duty cycle applications may

approach this minimum on-time limit and care should be

taken to ensure that:

ON MIN

OUT

()

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EXTERNAL

OSC

2.4V

10k

OSC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

PHASE

DETECTOR/

OSCILLATOR

FCB/SYNC

3738 F08

PLLFLTR

Figure 8. Phase-Locked Loop Block Diagram

LTC3738

3738f

If the duty cycle falls below what can be accommodated by

the minimum on-time, the IC will begin to skip every other

cycle, resulting in half-frequency operation. The output

voltage will continue to be regulated, but the ripple current

and ripple voltage will increase.

The minimum on-time for the IC is generally about 120ns.

However, as the peak sense voltage decreases the mini-

mum on-time gradually increases. This is of particular

concern in forced continuous applications with low ripple

current at light loads. If the duty cycle drops below the

minimum on-time limit in this situation, a significant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

If an application can operate close to the minimum on-

time limit, an inductor must be chosen that is low enough

in value to provide sufficient ripple amplitude to meet the

minimum on-time requirement.

As a general rule, keep

the

inductor ripple current equal to or greater than 30%

of I

OUT(MAX)

at V

IN(MAX)

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in DC (resistive) load

current. When a load step occurs, V

OUT

shifts by an

amount equal to ∆I

LOAD

• ESR, where ESR is the effective

series resistance of C

OUT

. ∆I

LOAD

also begins to charge or

discharge C

OUT

, generating the feedback error signal that

forces the regulator to adapt to the current change and

return V

OUT

to its steady-state value. During this recovery

time, V

OUT

can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the I

pin not only allows optimization of

control loop behavior, but also provides a DC coupled

and AC filtered closed-loop response test point. The DC

step, rise time and settling at this test point truly reflects

the closed-loop response. Assuming a predominantly

second order system, phase margin and/or damping

factor can be estimated using the percentage of overshoot

seen at this pin. The bandwidth can also be estimated by

examining the rise time at the pin. The I

external com-

ponents shown in the Figure 1 circuit will provide an

adequate starting point for most applications.

The I

series R

-C

filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.2 to 5 times their suggested values) to maximize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be decided

upon because the various types and values determine the

loop feedback factor gain and phase. An output current

pulse of 20% to 80% of full load current having a rise time

of <2µs will produce output voltage and I

pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop. The initial output voltage step,

resulting from the step change in output current, may not

be within the bandwidth of the feedback loop, so this signal

cannot be used to determine phase margin. This is why it

is better to look at the I

pin signal which is in the

feedback loop and is the filtered and compensated control

loop response. The gain of the loop will be increased by

increasing R

and the bandwidth of the loop will be

increased by decreasing C

. If R

is increased by the same

factor that C

is decreased, the zero frequency will be kept

the same, thereby keeping the phase the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual over-

all supply performance.

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with C

OUT

, causing a rapid drop in V

OUT

. No regulator can

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators 3-Phase VRM10/VRM9 Synch. Controller

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