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SX1231JIMLTRT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
www.semtech.comPage 13
SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
3. Chip Description
Semtech’s transceivers SX1231 and SX1231J share the architecture and functionnalities. For a complete description of the
feature set, please refer to [1]
4. Configuration and Status Registers
4.1. General Description
Table 9 Registers Summary
Address Register Name
Reset
(built-in)
Default
(recom
mended)
Description
0x00 RegFifo 0x00 FIFO read/write access
0x01 RegOpMode 0x04 Operating modes of the transceiver
0x02 RegDataModul 0x00 Data operation mode and Modulation settings
0x03 RegBitrateMsb 0x1A Bit Rate setting, Most Significant Bits
0x04 RegBitrateLsb 0x0B Bit Rate setting, Least Significant Bits
0x05 RegFdevMsb 0x00 Frequency Deviation setting, Most Significant Bits
0x06 RegFdevLsb 0x52 Frequency Deviation setting, Least Significant Bits
0x07 RegFrfMsb 0xE4 RF Carrier Frequency, Most Significant Bits
0x08 RegFrfMid 0xC0 RF Carrier Frequency, Intermediate Bits
0x09 RegFrfLsb 0x00 RF Carrier Frequency, Least Significant Bits
0x0A RegOsc1 0x41 RC Oscillators Settings
0x0B RegAfcCtrl 0x00 AFC control in low modulation index situations
0x0C RegLowBat 0x02 Low Battery Indicator Settings
0x0D RegListen1 0x92 Listen Mode settings
0x0E RegListen2 0xF5 Listen Mode Idle duration
0x0F RegListen3 0x20 Listen Mode Rx duration
0x10 RegVersion 0x23 Semtech ID relating the silicon revision
0x11 RegPaLevel 0x9F PA selection and Output Power control
0x12 RegPaRamp 0x09 Control of the PA ramp time in FSK mode
0x13 RegOcp 0x1A Over Current Protection control
0x14 Reserved14 0x40
-
0x15 Reserved15 0xB0
-
www.semtech.comPage 14
SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
0x16 Reserved16 0x7B
-
0x17 Reserved17 0x9B -
0x18 RegLna 0x08
0x88 LNA settings
0x19 RegRxBw 0x86
0x55 Channel Filter BW Control
0x1A RegAfcBw 0x8A
0x8B Channel Filter BW control during the AFC routine
0x1B RegOokPeak 0x40 OOK demodulator selection and control in peak mode
0x1C RegOokAvg 0x80 Average threshold control of the OOK demodulator
0x1D RegOokFix 0x06 Fixed threshold control of the OOK demodulator
0x1E RegAfcFei 0x10 AFC and FEI control and status
0x1F RegAfcMsb 0x00 MSB of the frequency correction of the AFC
0x20 RegAfcLsb 0x00 LSB of the frequency correction of the AFC
0x21 RegFeiMsb 0x00 MSB of the calculated frequency error
0x22 RegFeiLsb 0x00 LSB of the calculated frequency error
0x23 RegRssiConfig 0x02 RSSI-related settings
0x24 RegRssiValue 0xFF RSSI value in dBm
0x25 RegDioMapping1 0x00 Mapping of pins DIO0 to DIO3
0x26 RegDioMapping2 0x05
0x07 Mapping of pins DIO4 and DIO5, ClkOut frequency
0x27 RegIrqFlags1 0x80 Status register: PLL Lock state, Timeout, RSSI > Threshold...
0x28 RegIrqFlags2 0x00 Status register: FIFO handling flags, Low Battery detection...
0x29 RegRssiThresh 0xFF
0xE4 RSSI Threshold control
0x2A RegRxTimeout1 0x00 Timeout duration between Rx request and RSSI detection
0x2B RegRxTimeout2 0x00 Timeout duration between RSSI detection and PayloadReady
0x2C RegPreambleMsb 0x00 Preamble length, MSB
0x2D RegPreambleLsb 0x03 Preamble length, LSB
0x2E RegSyncConfig 0x98 Sync Word Recognition control
0x2F-0x36 RegSyncValue1-8 0x00
0x01 Sync Word bytes, 1 through 8
0x37 RegPacketConfig1 0x10 Packet mode settings
0x38 RegPayloadLength 0x40 Payload length setting
0x39 RegNodeAdrs 0x00 Node address
Address Register Name
Reset
(built-in)
Default
(recom
mended)
Description
www.semtech.comPage 15
SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
Note - Reset values are automatically refreshed in the chip at Power On Reset
- Default values are the Semtech recommended register values, optimizing the device operation
- Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 4
0x3A RegBroadcastAdrs 0x00 Broadcast address
0x3B RegAutoModes 0x00 Auto modes settings
0x3C RegFifoThresh 0x0F
0x8F Fifo threshold, Tx start condition
0x3D RegPacketConfig2 0x02 Packet mode settings
0x3E-0x4D RegAesKey1-16 0x00 16 bytes of the cypher key
0x4E RegTemp1 0x01 Temperature Sensor control
0x4F RegTemp2 0x00 Temperature readout
0x58 RegTestLna 0x1B Sensitivity boost
0x59 RegTestTcxo 0x09 TCXO or XTAL input setting
0x6F RegTestDagc 0x00
0x30 Fading Margin Improvement
0x71 RegTestAfc 0x00 AFC offset for low modulation index AFC
0x50 + RegTest - Internal test registers
Address Register Name
Reset
(built-in)
Default
(recom
mended)
Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

SX1231JIMLTRT

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Semtech
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IC RF TXRX ISM<1GHZ 24VQFN
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