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SX1231JIMLTRT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
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SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
RegPacketConfig1
(0x37)
7 PacketFormat rw 0 Defines the packet format used:
0 Æ Fixed length
1 Æ Variable length
6-5 DcFree rw 00 Defines DC-free encoding/decoding performed:
00 Æ None (Off)
01 Æ Manchester
10 Æ Whitening
11 Æ reserved
4 CrcOn rw 1 Enables CRC calculation/check (Tx/Rx):
0 Æ Off
1 Æ On
3 CrcAutoClearOff rw 0 Defines the behavior of the packet handler when CRC
check fails:
0 Æ Clear FIFO and restart new packet reception. No
PayloadReady interrupt issued.
1 Æ Do not clear FIFO. PayloadReady interrupt issued.
2-1 AddressFiltering rw 00 Defines address based filtering in Rx:
00 Æ None (Off)
01 Æ Address field must match NodeAddress
10 Æ Address field must match NodeAddress or
BroadcastAddress
11 Æ reserved
0 - rw 0 unused
RegPayloadLength
(0x38)
7-0 PayloadLength rw 0x40 If PacketFormat = 0 (fixed), payload length.
If PacketFormat = 1 (variable), max length in Rx, not used
in Tx.
RegNodeAdrs
(0x39)
7-0 NodeAddress rw 0x00 Node address used in address filtering.
RegBroadcastAdrs
(0x3A)
7-0 BroadcastAddress rw 0x00 Broadcast address used in address filtering.
RegAutoModes
(0x3B)
7-5 EnterCondition rw 000 Interrupt condition for entering the intermediate mode:
000 Æ None (AutoModes Off)
001 Æ Rising edge of FifoNotEmpty
010 Æ Rising edge of FifoLevel
011 Æ Rising edge of CrcOk
100 Æ Rising edge of PayloadReady
101 Æ Rising edge of SyncAddress
110 Æ Rising edge of PacketSent
111 Æ Falling edge of FifoNotEmpty (i.e. FIFO empty)
4-2 ExitCondition rw 000 Interrupt condition for exiting the intermediate mode:
000 Æ None (AutoModes Off)
001 Æ Falling edge of FifoNotEmpty (i.e. FIFO empty)
010 Æ Rising edge of FifoLevel or Timeout
011 Æ Rising edge of CrcOk or Timeout
100 Æ Rising edge of PayloadReady or Timeout
101 Æ Rising edge of SyncAddress or Timeout
110 Æ Rising edge of PacketSent
111 Æ Rising edge of Timeout
1-0 IntermediateMode rw 00 Intermediate mode:
00 Æ Sleep mode (SLEEP)
01 Æ Standby mode (STDBY)
10 Æ Receiver mode (RX)
11 Æ Transmitter mode (TX)
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SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
RegFifoThresh
(0x3C)
7 TxStartCondition rw 1
*
Defines the condition to start packet transmission :
0 Æ FifoLevel (i.e. the number of bytes in the FIFO
exceeds FifoThreshold)
1 Æ FifoNotEmpty (i.e. at least one byte in the FIFO)
6-0 FifoThreshold rw 0001111 Used to trigger FifoLevel interrupt.
RegPacketConfig2
(0x3D)
7-4 InterPacketRxDelay rw 0000 After PayloadReady occurred, defines the delay between
FIFO empty and the start of a new RSSI phase for next
packet. Must match the transmitter’s PA ramp-down time.
- Tdelay = 0 if InterpacketRxDelay >= 12
- Tdelay = (2
InterpacketRxDelay
) / BitRate otherwise
3 - rw 0 unused
2 RestartRx w 0 Forces the Receiver in WAIT mode, in Continuous Rx
mode.
Always reads 0.
1 AutoRxRestartOn rw 1 Enables automatic Rx restart (RSSI phase) after
PayloadReady occurred and packet has been completely
read from FIFO:
0 Æ Off. RestartRx can be used.
1 Æ On. Rx automatically restarted after
InterPacketRxDelay.
0 AesOn rw 0 Enable the AES encryption/decryption:
0 Æ Off
1 Æ On (payload limited to 66 bytes maximum)
RegAesKey1
(0x3E)
7-0 AesKey(127:120) w 0x00
1
st
byte of cipher key (MSB byte)
RegAesKey2
(0x3F)
7-0 AesKey(119:112) w 0x00
2
nd
byte of cipher key
RegAesKey3
(0x40)
7-0 AesKey(111:104) w 0x00
3
rd
byte of cipher key
RegAesKey4
(0x41)
7-0 AesKey(103:96) w 0x00
4
th
byte of cipher key
RegAesKey5
(0x42)
7-0 AesKey(95:88) w 0x00
5
th
byte of cipher key
RegAesKey6
(0x43)
7-0 AesKey(87:80) w 0x00
6
th
byte of cipher key
RegAesKey7
(0x44)
7-0 AesKey(79:72) w 0x00
7
th
byte of cipher key
RegAesKey8
(0x45)
7-0 AesKey(71:64) w 0x00
8
th
byte of cipher key
RegAesKey9
(0x46)
7-0 AesKey(63:56) w 0x00
9
th
byte of cipher key
RegAesKey10
(0x47)
7-0 AesKey(55:48) w 0x00
10
th
byte of cipher key
RegAesKey11
(0x48)
7-0 AesKey(47:40) w 0x00
11
th
byte of cipher key
RegAesKey12
(0x49)
7-0 AesKey(39:32) w 0x00
12
th
byte of cipher key
RegAesKey13
(0x4A)
7-0 AesKey(31:24) w 0x00
13
th
byte of cipher key
www.semtech.comPage 27
SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
4.7. Temperature Sensor Registers
Table 15 Temperature Sensor Registers
4.8. Test Registers
Table 16 Test Registers
RegAesKey14
(0x4B)
7-0 AesKey(23:16) w 0x00
14
th
byte of cipher key
RegAesKey15
(0x4C)
7-0 AesKey(15:8) w 0x00
15
th
byte of cipher key
RegAesKey16
(0x4D)
7-0 AesKey(7:0) w 0x00
16
th
byte of cipher key (LSB byte)
Name
(Address)
Bits Variable Name Mode
Default
Value
Description
RegTemp1
(0x4E)
7-4 - r 0000 unused
3 TempMeasStart w 0 Triggers the temperature measurement when set. Always
reads 0.
2 TempMeasRunning r 0 Set to 1 while the temperature measurement is running.
Toggles back to 0 when the measurement has completed.
The receiver can not be used while measuring
temperature
1-0 - r 01 unused
RegTemp2
(0x4F)
7-0 TempValue r - Measured temperature
-1°C per Lsb
Needs calibration for accuracy
Name
(Address)
Bits Variable Name Mode
Default
Value
Description
RegTestLna
(0x58)
7-0 SensitivityBoost rw 0x1B High sensitivity or normal sensitivity mode:
0x1B Æ Normal mode
0x2D Æ High sensitivity mode
RegTestTcxo
(0x59)
7-0 TcxoOn rw 0x09 Selects XTAL or TCXO input:
0x09 Æ Normal XTAL mode
0x19 Æ Clipped sine TCXO input
RegTestDagc
(0x6F)
7-0 ContinuousDagc rw 0x30
*
Fading Margin Improvement, refer to 3.5.4
0x00 Æ Normal mode
0x20 Æ Improved margin, use if AfcLowBetaOn=1
0x30 Æ Improved margin, use if AfcLowBetaOn=0
RegTestAfc
(0x71)
7-0 LowBetaAfcOffset rw 0x00 AFC offset set for low modulation index systems, used if
AfcLowBetaOn=1.
Offset = LowBetaAfcOffset x 488 Hz
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SX1231JIMLTRT

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Manufacturer:
Semtech
Description:
IC RF TXRX ISM<1GHZ 24VQFN
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