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SX1231JIMLTRT

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www.semtech.comPage 4
SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
Acronyms
BOM Bill Of Materials LSB Least Significant Bit
BR Bit Rate MSB Most Significant Bit
BW Bandwidth NRZ Non Return to Zero
CCITT Comité Consultatif International
Téléphonique et Télégraphique - ITU
OOK On Off Keying
CRC Cyclic Redundancy Check PA Power Amplifier
DAC Digital to Analog Converter PCB Printed Circuit Board
ETSI European Telecommunications Standards
Institute
PLL Phase-Locked Loop
FCC Federal Communications Commission POR Power On Reset
Fdev Frequency Deviation RBW Resolution BandWidth
FIFO First In First Out RF Radio Frequency
FIR Finite Impulse Response RSSI Received Signal Strength Indicator
FS Frequency Synthesizer Rx Receiver
FSK Frequency Shift Keying SAW Surface Acoustic Wave
GUI Graphical User Interface SPI Serial Peripheral Interface
IC Integrated Circuit SR Shift Register
ID IDentificator Stby Standby
IF Intermediate Frequency Tx Transmitter
IRQ Interrupt ReQuest uC Microcontroller
ITU International Telecommunication Union VCO Voltage Controlled Oscillator
LFSR Linear Feedback Shift Register XO Crystal Oscillator
LNA Low Noise Amplifier XOR eXclusive OR
LO Local Oscillator
www.semtech.comPage 5
SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
This product datasheet contains a detailed description of the SX1231J performance and functionality. Please consult the
Semtech website
www.semtech.com for the latest updates or errata.
1. General Description
The SX1231J is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The
SX1231J's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high
level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended
for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-directional
RF links, and where stable and constant RF performance is required over the full operating range of the device down to
1.8V.
Coupled with a link budget in excess of 135 dB, the advanced system features of the SX1231J include a 66 byte TX/RX
FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly
enhance system flexibility whilst at the same time significantly reducing MCU requirements.
The SX1231J complies with Japanese ARIB regulatory requirements and is available in a 5x 5 mm QFN 24 lead package.
1.1. Simplified Block Diagram
Figure 1. Block Diagram
LNA
Single to
Differential
Mixers
Σ/Δ
Modulators
Decimation and
& Filtering
Demodulator &
Bit Synchronizer
Interpolation
& Filtering
Modulator
Packet Engine & 66 Bytes FIFO
Control Registers - Shift Registers - SPI Interface
RSSI AFC
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
XTAL
PA0
PA1&2
Tank
Inductor
Loop
Filter
RFIO
PA_BOOST
RESET
GND
Power Distribution System
VBAT1&2 VR_ANA VR_DIG
VR_PA
Ramp &
Control
RC
Oscillator
Frequency Synthesis
Receiver Blocks
Transmitter Blocks
Control Blocks
Primarily Analog
Primarily Digital
GND
SPI
DIO0
RXTX
DIO1
DIO2
DIO3
DIO4
DIO5
www.semtech.comPage 6
SX1231J
WIRELESS & SENSING
DATASHEET
Rev 2 - April 2012
1.2. Pin and Marking Diagram
The following diagram shows the pin arrangement of the SX1231J, top view.
Figure 2. Pin Diagram (not to scale)
Figure 3. Marking Diagram
Notes yyww refers to the date code
xxxxxx refers to the lot number
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SX1231JIMLTRT

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Manufacturer:
Semtech
Description:
IC RF TXRX ISM<1GHZ 24VQFN
Lifecycle:
New from this manufacturer.
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