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SC16C2550BIB48,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 10 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.2 Internal registers
The SC16C2550B provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 5. The UART registers function as data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control
Register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM) and a
user-accessible Scratchpad Register (SPR).
[1] These registers are accessible only when LCR[7] is a logic 0.
[2] These registers are accessible only when LCR[7] is a logic 1.
Table 4. Serial port selection
Chip Select Function
CSA, CSB = 1 none
CSA = 0 UART channel A
CSB = 0 UART channel B
Table 5. Internal registers decoding
A2 A1 A0 READ mode WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)
[1]
0 0 0 Receive Holding Register Transmit Holding Register
0 0 1 Interrupt Enable Register Interrupt Enable Register
0 1 0 Interrupt Status Register FIFO Control Register
0 1 1 Line Control Register Line Control Register
1 0 0 Modem Control Register Modem Control Register
1 0 1 Line Status Register n/a
1 1 0 Modem Status Register n/a
1 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
0 0 0 LSB of Divisor Latch LSB of Divisor Latch
0 0 1 MSB of Divisor Latch MSB of Divisor Latch
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 11 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.3 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. The user can set the receive trigger level via FCR bits 7:6, but not the transmit
trigger level. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
6.4 Hardware/software and time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit1=1,theSC16C2550B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR register provides the current singular highest priority
interrupt only. A condition can exist where a higher priority interrupt may mask the lower
priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority
interrupt(s) be reflected in the status register. Servicing the interrupt without investigating
further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C2550B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center
of each stop bit received or each time the Receive Holding Register (RHR) is read. The
actual time-out value is 4 character time, including data information length, start bit, parity
bit and the size of stop bit, that is, 1×, 1.5× or 2× bit times.
Table 6. Flow control mechanism
Selected trigger level (characters) INTn pin activation
11
44
88
14 14
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 12 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.5 Programmable baud rate generator
The SC16C2550B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC16C2550B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable baud rate generator is capable of
operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary
to use full rail swing on the clock input. The SC16C2550B can be configured for internal or
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins.
Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates (see Table 7).
The generator divides the input 16× clock by any divisor from 1 to (2
16
− 1). The
SC16C2550B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in Table 7 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
Fig 6. Crystal oscillator connection
002aaa870
C2
47 pF
XTAL1 XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1 XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

SC16C2550BIB48,157

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Buy SC16C2550BIB48,157
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 2CH
Lifecycle:
New from this manufacturer.
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