SC16C2550BIB48,157 Datasheet SC16C2550BIB48,151, SC16C2550BIA44,518, SC16C2550BIBS,128 | P19-P21

Product data sheet Rev. 05 — 12 January 2009 19 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C2550B provides four levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. A lower level interrupt may be seen after servicing the

higher level interrupt and re-reading the interrupt status bits. Table 12 “Interrupt source”

shows the data values (bits 3:0) for the four prioritized interrupt levels and the interrupt

sources associated with each of these interrupt levels.

1 FCR[1] RCVR FIFO reset.

logic 0 = Receive FIFO not reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the Receive Shift Register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFOs enabled.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to or they will not be programmed.

Table 11. RCVR trigger levels

FCR[7] FCR[6] RX FIFO trigger level

0001

0104

1008

1114

Table 10. FIFO Control Register bits description

…continued

Bit Symbol Description

Table 12. Interrupt source

Priority

level

ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1 0 1 1 0 LSR (Receiver Line Status Register)

2 0 1 0 0 RXRDY (Received Data Ready)

2 1 1 0 0 RXRDY (Receive Data Time-out)

3 0 0 1 0 TXRDY (Transmitter Holding Register empty)

4 0 0 0 0 MSR (Modem Status Register)

Product data sheet Rev. 05 — 12 January 2009 20 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits and the parity are selected by writing the

appropriate bits in this register.

Table 13. Interrupt Status Register bits description

Bit Symbol Description

7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not

being used in the 16C450 mode. They are set to a logic 1 when the

FIFOs are enabled in the SC16C2550B mode.

logic 0 or cleared = default condition

5:4 ISR[5:4] not used

3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt

at interrupt priority levels 1, 2 and 3 (see

Table 12).

logic 0 or cleared = default condition

0 ISR[0] INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as

a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

Table 14. Line Control Register bits description

Bit Symbol Description

7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6 LCR[6] Set break. When enabled, the Break control bit causes a break condition

to be transmitted (the TX output is forced to a logic 0 state). This

condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3 LCR[5:3] Programs the parity conditions (see

Table 15)

2 LCR[2] Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length (see

Table 16).

logic 0 or cleared = default condition

1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see

Table 17).

logic 0 or cleared = default condition

Table 15. LCR[5:3] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

X X 0 no parity

X 0 1 odd parity

0 1 1 even parity

0 0 1 forced parity ‘1’

1 1 1 forced parity ‘0’

Product data sheet Rev. 05 — 12 January 2009 21 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 16. LCR[2] stop bit length

LCR[2] Word length (bits) Stop bit length (bit times)

0 5, 6, 7, 8 1

15 1

⁄

1 6, 7, 8 2

Table 17. LCR[1:0] word length

LCR[1] LCR[0] Word length (bits)

005

016

107

118

Table 18. Modem Control Register bits description

Bit Symbol Description

7:5 MCR[7:5] reserved; set to ‘0’

4 MCR[4] Loopback. Enable the local Loopback mode (diagnostics). In this mode the

transmitter output (

TX) and the receiver input (RX), CTS, DSR, CD and RI

are disconnected from the SC16C2550B I/O pins. Internally the modem

data and control pins are connected into a loopback data conﬁguration

(see

Figure 7). In this mode, the receiver and transmitter interrupts remain

fully operational. The Modem Control Interrupts are also operational, but

the interrupts’ sources are switched to the lower four bits of the Modem

Control. Interrupts continue to be controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

3 MCR[3]

OP2/INT enable

logic 0 = forces INT (A, B) outputs to the 3-state mode and sets

OP2 to a

logic 1 (normal default condition)

logic 1 = forces the INT (A, B outputs to the active mode and sets

OP2 to

a logic 0

2 MCR[2] (

OP1). OP1A/OP1B are not available as an external signal in the

SC16C2550B. This bit is instead used in the Loopback mode only. In the

Loopback mode, this bit is used to write the state of the modem

interface signal.

1 MCR[1]

RTS

logic 0 = force

RTS output to a logic 1 (normal default condition)

logic 1 = force

RTS output to a logic 0

0 MCR[0]

DTR

logic 0 = force

DTR output to a logic 1 (normal default condition)

logic 1 = force

DTR output to a logic 0

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SC16C2550BIB48,157

Mfr. #:

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Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 16CB 2.5V-5V 2CH

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SC16C2550BIB48,157

SC16C2550BIB48,157

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