SC16C2550BIB48,157 Datasheet SC16C2550BIB48,151, SC16C2550BIA44,518, SC16C2550BIBS,128 | P16-P18

Product data sheet Rev. 05 — 12 January 2009 16 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

prevent false starts. On the falling edge of a start or false start bit, an internal receiver

counter starts counting clocks at the 16× clock rate. After 7

⁄

clocks, the start bit time

should be shifted to the center of the start bit. At this time the start bit is sampled and if it

is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver

from assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA, INTB output pins.

Table 9. Interrupt Enable Register bits description

Bit Symbol Description

7:4 IER[7:4] not used

3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a

modem status change as reﬂected in MSR[3:0].

logic 0 = disable the Modem Status Register interrupt (normal default

condition)

logic 1 = enable the Modem Status Register interrupt

2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a

receive data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

1 IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will

be issued whenever the THR is empty and is associated with LSR[5]. In the

FIFO modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0 IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will be issued

when the RHR has data or is cleared when the RHR is empty. In the FIFO

mode, this interrupt will be issued when the FIFO has reached the

programmed trigger level or is cleared when the FIFO drops below the

trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

Product data sheet Rev. 05 — 12 January 2009 17 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR register or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2550B in the FIFO polled

mode of operation. In this mode, interrupts are not generated and the user must poll the

LSR register for TX and/or RX data status. Since the receiver and transmitter have

separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation and is similar to

the 16C450 mode. Transmit Ready (TXRDYn) on PLCC44 and LQFP48 packages will go

to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready

(RXRDYn) on PLCC44 and LQFP48 packages will go to a logic 0 whenever the Receive

Holding Register (RHR) is loaded with a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is empty. TXRDYn on PLCC44 and LQFP48 packages remains a logic 0

as long as one empty FIFO location is available. The receive interrupt is set when the

receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll

Product data sheet Rev. 05 — 12 January 2009 18 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and

LQFP48 packages transitions LOW when the FIFO reaches the trigger level and

transitions HIGH when the FIFO empties.

7.3.2 FIFO mode

Table 10. FIFO Control Register bits description

Bit Symbol Description

7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

logic 0 (or cleared) = normal default condition

logic 1 = RX trigger level

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to be

loaded until it is full. Refer to

Table 11.

5:4 FCR[5:4] Not used; initialized to logic 0.

3 FCR[3] DMA mode select.

logic 0 = set DMA mode ‘0’

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C2550B is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0) and when there are no

characters in the transmit FIFO or Transmit Holding Register, the

TXRDYn

pin in PLCC44 or LQFP48 packages will be a logic 0. Once active, the

TXRDYn pin will go to a logic 1 after the ﬁrst character is loaded into the

Transmit Holding Register.

Receive operation in mode ‘0’: When the SC16C2550B is in mode ‘0’

(FCR[0] = logic 0) or in the FIFO mode (FCR[3] = logic 0) and there is at

least one character in the receive FIFO, the

RXRDYn pin will be a logic 0.

Once active, the

RXRDYn pin on PLCC44 and LQFP48 packages will go

to a logic 1 when there are no more characters in the receiver.

Transmit operation in mode ‘1’: When the SC16C2550B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin on PLCC44

and LQFP48 packages will be a logic 1 when the transmit FIFO is

completely full. It will be a logic 0 if one or more FIFO locations are empty.

Receive operation in mode ‘1’: When the SC16C2550B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached

or a Receive Time-out has occurred, the

RXRDYn pin on PLCC44 and

LQFP48 packages will go to a logic 0. Once activated, it will go to a logic 1

after there are no more characters in the FIFO.

2 FCR[2] XMIT FIFO reset.

logic 0 = Transmit FIFO not reset (normal default condition).

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the Transmit Shift Register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

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SC16C2550BIB48,157

Mfr. #:

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Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 16CB 2.5V-5V 2CH

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SC16C2550BIB48,157

SC16C2550BIB48,157

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