SC16C2550BIB48,157 Datasheet SC16C2550BIB48,151, SC16C2550BIA44,518, SC16C2550BIBS,128 | P7-P9

Product data sheet Rev. 05 — 12 January 2009 7 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

RESET 24 35 39 36 I Reset (active HIGH). A logic 1 on this pin will reset the internal

registers and all the outputs. The UART transmitter output and

the receiver input will be disabled during reset time. (See

Section 7.10 “SC16C2550B external reset condition” for

initialization details.)

RXRDYA- - 34 31 O Receive Ready A, B (active LOW). This function is associated

with PLCC44 and LQFP48 packages only. This function

provides the RX FIFO/RHR status for individual receive

channels (A-B).

RXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the receive data FIFOs. A logic 0

indicates there is a receive data to read/upload, that is, receive

ready status with one or more RX characters available in the

FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty

or when the programmed trigger level has not been reached.

This signal can also be used for single mode transfers (DMA

mode 0).

RXRDYB - - 23 18 O

TXRDYA - - 1 43 O Transmit Ready A, B (active LOW). This function is

associated with PLCC44 and LQFP48 packages only. These

outputs provide the TX FIFO/THR status for individual transmit

channels (A, B).

TXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the transmit data FIFOs. An

individual channel’s

TXRDYA, TXRDYB buffer ready status is

indicated by logic 0, that is, at least one location is empty and

available in the FIFO or THR. This pin goes to a logic 1 (DMA

mode 1) when there are no more empty locations in the FIFO

or THR. This signal can also be used for single mode transfers

(DMA mode 0).

TXRDYB - - 12 6 O

26 40 44 42 I Power supply input.

XTAL1 10 16 18 13 I Crystal or external clock input. Functions as a crystal input

or as an external clock input. A crystal can be connected

between this pin and XTAL2 to form an internal oscillator

circuit. Alternatively, an external clock can be connected to this

pin to provide custom data rates. (See

Section 6.5

“Programmable baud rate generator”.) See Figure 6.

XTAL2 11 17 19 14 O Output of the crystal oscillator or buffered clock. (See also

XTAL1.) Crystal oscillator output or buffered clock output.

Should be left open if an external clock is connected to XTAL1.

For extended frequency operation, this pin should be tied to

via a 2 kΩ resistor.

CDA - 38 42 40 I Carrier Detect (active LOW). These inputs are associated

with individual UART channels A through B. A logic 0 on this

pin indicates that a carrier has been detected by the modem for

that channel.

CDB - 19 21 16 I

CTSA 25 36 40 38 I Clear to Send (active LOW). These inputs are associated with

individual UART channels, A through B. A logic 0 on the

CTSn

pin indicates the modem or data set is ready to accept transmit

data from the SC16C2550B. Status can be tested by reading

MSR[4]. This pin has no effect on the UART’s transmit or

receive operation.

CTSB 16 25 28 23 I

Table 3. Pin description

…continued

Symbol Pin Type Description

HVQFN32 DIP40 PLCC44 LQFP48

Product data sheet Rev. 05 — 12 January 2009 8 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

DSRA - 37 41 39 I Data Set Ready (active LOW). These inputs are associated

with individual UART channels, A through B. A logic 0 on this

pin indicates the modem or data set is powered-on and is ready

for data exchange with the UART. This pin has no effect on the

UART’s transmit or receive operation.

DSRB - 22 25 20 I

DTRA - 33 37 34 O Data Terminal Ready (active LOW). These outputs are

associated with individual UART channels, A through B.

A logic 0 on this pin indicates that the SC16C2550B is

powered-on and ready. This pin can be controlled via the

Modem Control Register. Writing a logic 1 to MCR[0] will set

the

DTRn output to logic 0, enabling the modem. This pin will

be a logic 1 after writing a logic 0 to MCR[0] or after a reset.

This pin has no effect on the UART’s transmit or receive

operation.

DTRB - 34 38 35 O

RIA - 39 43 41 I Ring Indicator (active LOW). These inputs are associated

with individual UART channels, A through B. A logic 0 on this

pin indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on this input pin will generate

an interrupt.

RIB - 23 26 21 I

RTSA 23 32 36 33 O Request to Send (active LOW). These outputs are associated

with individual UART channels, A through B. A logic 0 on the

RTSn pin indicates the transmitter has data ready and waiting

to send. Writing a logic 1 in the Modem Control Register

MCR[1] will set this pin to a logic 0, indicating data is available.

After a reset this pin will be set to a logic 1. This pin has no

effect on the UART’s transmit or receive operation.

RTSB 15 24 27 22 O

RXA 4 10 11 5 I Receive data A, B. These inputs are associated with individual

serial channel data to the SC16C2550B receive input circuits,

A and B. The RXn signal will be a logic 1 during reset, idle (no

data) or when the transmitter is disabled. During the local

Loopback mode, the RXn input pin is disabled and TX data is

connected to the UART RX input, internally.

RXB 3 9 10 4 I

TXA 5 11 13 7 O Transmit data A, B. These outputs are associated with

individual serial transmit channel data from the SC16C2550B.

The TXn signal will be a logic 1 during reset, idle (no data) or

when the transmitter is disabled. During the local Loopback

mode, the TXn output pin is disabled and TX data is internally

connected to the UART RX input.

TXB 6 12 14 8 O

n.c. - - - 12, 24,

25, 37

- not connected

Table 3. Pin description

…continued

Symbol Pin Type Description

HVQFN32 DIP40 PLCC44 LQFP48

Product data sheet Rev. 05 — 12 January 2009 9 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6. Functional description

The SC16C2550B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C2550B represents such

an integration with greatly enhanced features. The SC16C2550B is fabricated with an

advanced CMOS process.

The SC16C2550B is an upward solution that provides a dual UART capability with

16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The

SC16C2550B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C2550B by the transmit and receive FIFOs. This allows the external processor to

handle more networking tasks within a given time. For example, the ST16C2450 without a

receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a

character length of 11 bits, including start/stop bits at 115.2 kbit/s). This means the

external CPU will have to service the receive FIFO less than every 100 microseconds.

However, with the 16-byte FIFO in the SC16C2550B, the data buffer will not require

unloading/loading for 1.53 ms. This increases the service interval, giving the external CPU

additional time for other applications and reducing the overall UART interrupt servicing

time. In addition, the four selectable receive FIFO trigger interrupt levels are uniquely

provided for maximum data throughput performance especially when operating in a

multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement

of the external controlling CPU, increases performance and reduces power consumption.

The SC16C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a

crystal or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbit/s.

The rich feature set of the SC16C2550B is available through internal registers. Selectable

receive FIFO trigger levels, selectable TX and RX baud rates and modem interface

controls are all standard features. Following a power-on reset or an external reset, the

SC16C2550B is software compatible with the previous generation, ST16C2450.

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C2550B package and an external serial device. A

logic 0 on chip select pins CSA and/or CSB allows the user to conﬁgure, send data,

and/or receive data via UART channels A through B. Individual channel select functions

are shown in Table 4.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P43

SC16C2550BIB48,157

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Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 16CB 2.5V-5V 2CH

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SC16C2550BIB48,157

SC16C2550BIB48,157

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