74HC_HCT7403_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 21 September 2012 17 of 32
NXP Semiconductors
74HC7403-Q100; 74HCT7403-Q100
4-bit x 64-word FIFO register; 3-state
Measurement points are given in Table 7.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
With FIFO empty; SO
is held HIGH in anticipation
(1) FIFO is initially empty. SO
is held HIGH.
(2) SI pulse; loads data into FIFO and initiates ripple through process
(3) DOR flag signals the arrival of valid data at the output stage
(4) Output transition; data arrives at output stage after the specified propagation delay between the rising and falling edge of the
DOR pulse to the Qn output
(5) DOR goes LOW; data shift-out is completed, FIFO is empty again
(6) SO
set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty
Fig 10. Ripple through delay SI input to DOR output, propagation delay DOR input to Qn outputs and the DOR
pulse width
6,,1387
PJD
4Q287387
'25287387
ULSSOHWKURXJK
GHOD\
62,1387
9
0
9
0
9
0
W
:
W
3/+
W
3+/
W
3/+
Measurement points are given in Table 7.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Shift-in operation; high speed burst mode
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR
status flag is a “don’t care” condition, and a shift-in pulse can be applied regardless of the flag. An SI pulse which would
overflow the storage capacity of the FIFO is ignored.
Fig 11. Shift-in (SI) pulse width and maximum frequency (SI)
,1387
,1387
87
9
0
W
:
PD[
