74HC_HCT7403_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 21 September 2012 7 of 32
NXP Semiconductors
74HC7403-Q100; 74HCT7403-Q100
4-bit x 64-word FIFO register; 3-state
I
CC
supply current V
I
=V
CC
or GND; I
O
=0A;
V
CC
=6.0V
- - 50 - 500 - 1000 A
C
I
input
capacitance
-3.5- pF
74HCT7403-Q100
V
IH
HIGH-level
input voltage
V
CC
= 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
V
OH
HIGH-level
output voltage
V
I
=V
IH
or V
IL
; V
CC
=4.5V
I
O
= 20 A 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 8 mA 3.98 4.32 - 3.84 - 3.7 - V
V
OL
LOW-level
output voltage
V
I
=V
IH
or V
IL
; V
CC
=4.5V
I
O
=20A - 0 0.1 - 0.1 - 0.1 V
I
O
= 8 mA - 0.15 0.26 - 0.33 - 0.4 V
I
I
input leakage
current
V
I
=V
CC
or GND;
V
CC
=5.5V
--0.1 - 1.0 - 1.0 A
I
OZ
OFF-state
output current
V
I
=V
IH
or V
IL
; V
CC
=5.5V;
V
O
=V
CC
or GND per input
pin; other inputs at V
CC
or
GND; I
O
=0A
--0.5 - 5.0 - 10 A
I
CC
supply current V
I
=V
CC
or GND; I
O
=0A;
V
CC
=5.5V
- - 50 - 500 - 1000 A
I
CC
additional
supply current
V
I
=V
CC
2.1 V;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V;
I
O
=0A
per input pin; Dn inputs - 75 270 - 338 - 368 A
per input pin; OE
input - 100 360 - 450 - 490 A
per input pin; SI input - 150 540 - 675 - 735 A
per input pin; MR
input - 150 540 - 675 - 735 A
per input pin; SO
input - 150 540 - 675 - 735 A
C
I
input
capacitance
-3.5- pF
Table 5. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT7403_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 21 September 2012 8 of 32
NXP Semiconductors
74HC7403-Q100; 74HCT7403-Q100
4-bit x 64-word FIFO register; 3-state
11. Dynamic characteristics
Table 6. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC7403-Q100
t
pd
propagation
delay
MR to DIR or DOR; see
Figure 8
[1]
V
CC
= 2.0 V - 69 210 - 265 - 315 ns
V
CC
= 4.5 V - 25 42 - 53 - 63 ns
V
CC
= 6.0 V - 20 36 - 45 - 54 ns
SI to DIR; see Figure 6
[1]
V
CC
= 2.0 V - 66 205 - 255 - 310 ns
V
CC
= 4.5 V - 24 41 - 51 - 62 ns
V
CC
=5V; C
L
=15pF - 15 - - - - - ns
V
CC
= 6.0 V - 19 35 - 43 - 53 ns
SO
to DOR; see Figure 9
[1]
V
CC
= 2.0 V - 94 290 - 365 - 435 ns
V
CC
= 4.5 V - 34 58 - 73 - 87 ns
V
CC
=5V; C
L
=15pF - 15 - - - - - ns
V
CC
= 6.0 V - 27 49 - 62 - 74 ns
DOR to Qn; see Figure 10
[1]
V
CC
= 2.0 V - 11 35 - 45 - 55 ns
V
CC
= 4.5 V - 4 7 - 9 - 11 ns
V
CC
= 6.0 V - 3 6 - 8 - 9 ns
SO
to Qn; see Figure 14
[1]
V
CC
= 2.0 V - 105 325 - 406 - 488 ns
V
CC
= 4.5 V - 38 65 - 81 - 98 ns
V
CC
= 6.0 V - 30 55 - 69 - 83 ns
t
PHL
HIGH to
LOW
propagation
delay
MR to Qn; see Figure 8
V
CC
= 2.0 V - 52 160 - 200 - 240 ns
V
CC
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
= 6.0 V - 15 27 - 34 - 41 ns
t
PLH
LOW to
HIGH
propagation
delay
SI to DOR; see Figure 10
[5]
V
CC
= 2.0 V - 2.2 7 - 8.8 - 10.5 ns
V
CC
= 4.5 V - 0.8 1.4 - 1.8 - 2.1 ns
V
CC
= 6.0 V - 0.6 1.2 - 1.5 - 1.8 ns
SO
to DIR; see Figure 7
[6]
V
CC
= 2.0 V - 2.8 9 - 11.2 - 13.5 ns
V
CC
= 4.5 V - 1.0 1.8 - 2.2 - 2.7 ns
V
CC
= 6.0 V - 0.8 1.5 - 1.9 - 2.3 ns
74HC_HCT7403_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 21 September 2012 9 of 32
NXP Semiconductors
74HC7403-Q100; 74HCT7403-Q100
4-bit x 64-word FIFO register; 3-state
t
en
enable time OE to Qn; see Figure 16
[2]
V
CC
= 2.0 V - 44 150 - 190 - 225 ns
V
CC
= 4.5 V - 16 30 - 38 - 45 ns
V
CC
= 6.0 V - 13 26 - 32 - 38 ns
t
dis
disable time OE to Qn; see Figure 16
[3]
V
CC
= 2.0 V - 50 150 - 190 - 225 ns
V
CC
= 4.5 V - 18 30 - 38 - 45 ns
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
t
t
transition
time
Qn; see Figure 14
[4]
V
CC
= 2.0 V - 14 60 - 75 - 90 ns
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
V
CC
= 6.0 V - 4 10 - 13 - 15 ns
t
W
pulse width SI HIGH or LOW;
see Figure 6
V
CC
= 2.0 V 35 11 - 45 - 55 - ns
V
CC
= 4.5 V 7 4 - 9 - 11 - ns
V
CC
= 6.0 V 6 3 - 8 - 9 - ns
SO
HIGH or LOW;
see Figure 9
V
CC
= 2.0 V 70 22 - 90 - 105 - ns
V
CC
= 4.5 V 14 8 - 18 - 21 - ns
V
CC
= 6.0 V 12 6 - 15 - 18 - ns
DIR HIGH; see Figure 7
V
CC
= 2.0 V 10 41 130 8 165 8 195 ns
V
CC
= 4.5 V 5 15 26 4 33 4 39 ns
V
CC
= 6.0 V 4 12 22 3 28 3 23 ns
DOR HIGH; see Figure 10
V
CC
= 2.0 V 14 52 160 12 200 12 240 ns
V
CC
= 4.5 V 7 19 32 6 40 6 48 ns
V
CC
= 6.0 V 6 15 27 5 34 5 41 ns
MR
LOW; see Figure 8
V
CC
= 2.0 V 120 39 - 150 - 180 - ns
V
CC
= 4.5 V 24 14 - 30 - 36 - ns
V
CC
= 6.0 V 20 11 - 26 - 31 - ns
t
rec
recovery
time
MR to SI; see Figure 15
V
CC
= 2.0 V 80 24 - 100 - 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 7 - 17 - 20 - ns
Table 6. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 17.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max

74HC7403D-Q100,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC FIFO REGISTER 4X64 3ST 16SOIC
Lifecycle:
New from this manufacturer.
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