ICS8714004DKI REVISION A MARCH 24, 2014 3 ©2014 Integrated Device Technology, Inc.
ICS8714004I Data Sheet FemtoCLock
®
Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number Name Type Description
1, 11, 22, 30, 35 V
DD
Power Core supply pins.
2 OE_MLVDS Input Pullup
Active High Output Enable. When HIGH, the M-LVDS output driver is active and
provides a buffered copy of reference clock applied the CLK, nCLK input to the
MLVDS, nMLVDS output pins. The MLVDS, nMLVDS frequency equals the CLK,
nCLK frequency divided by the PDIV Divider value (selectable ÷1, ÷4, ÷5, ÷8).
When LOW, the M-LVDS output driver is placed into a High Impedance state and
the MLVDS, nMLVDS pins can accept a differential input. LVCMOS/LVTTL
interface levels.
3 MLVDS I/O
Non-Inverting M-LVDS input/output. The input/output state is determined by the
OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives the
non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input and
can accept the following differential input levels: M-LVDS, LVDS, LVPECL,
HSTL, HCSL.
4 nMLVDS I/O
Inverting M-LVDS input/output. The input/output state is determined by the
OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives the
inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input and can
accept the following differential input levels: M-LVDS, LVDS, LVPECL, HSTL,
HCSL.
5 PLL_SEL Input Pullup
PLL select. Determines if the PLL is in bypass or enabled mode (default). In
enabled mode, the output frequency = VCO frequency/QDIV divider. In bypass
mode, the output frequency = reference clock frequency/ (PDIV*QDIV).
LVCMOS/LVTTL interface levels.
6 FBO_DIV Input Pulldown
Output Divider Control for the feedback output pair, FBOUT, nFBOUT. Refer to
Table 3D. LVCMOS/LVTTL interface levels.
7 MR Input Pulldown
Active High master reset. When logic HIGH, the internal dividers are reset
causing the Qx, nQx outputs to drive High Impedance. Note that assertion of MR
overrides the OE[1:0] control pins and all outputs are disabled. When logic LOW,
the internal dividers are enabled and the state of the outputs is determined by
OE[1:0]. MR must be asserted on power-up to ensure outputs phase aligned.
LVCMOS/LVTTL interface levels.
8 OE0 Input Pullup
Output Enable. Together with OE1, determines the output state of the outputs
with the default state: all output pairs switching. Refer to Table 3B Truth table.
LVCMOS/LVTTL Interface levels.
9 OE1 Input Pullup
Output Enable. Together with OE0, determines the output state of the outputs
with the default state: all output pairs switching. Refer to Table 3B Truth table.
LVCMOS/LVTTL Interface levels
10, 16, 27 GND Power Power supply ground.
12 FBI_DIV0 Input Pullup
Feedback Input Divide Select 0. Together with FBI_DIV1, determines the
feedback input divider value. Refer to Table 3C. LVCMOS/LVTTL interface
levels.
13 FBI_DIV1 Input Pullup
Feedback Input Divide Select 1. Together with FBI_DIV0, determines the
feedback input divider value. Refer to Table 3C. LVCMOS/LVTTL interface
levels.
14 nFBIN Input
Pullup/
Pulldown
Inverted differential feedback input to the PLL for regenerating clocks with “Zero
Delay.”
15 FBIN Input Pulldown
Non-inverted differential feedback input to the PLL for regenerating clocks with
“Zero Delay.”
