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8714004DKILF
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P31
ICS8714004DKI REVISION A MARCH 24, 2014
1
0
©2014 Integrated Devi
ce Techno
logy, Inc.
ICS8714004I Data Sheet
FemtoCLock
®
Zero Delay Buffer/Cloc
k Generator for PCI Express™ a
nd Ethernet
Typical Phase Noise at 125MHz
Noise P
ower
dBc
Hz
Offset F
requency
(Hz)
ICS8714004DKI REVISION A MARCH 24, 2014
1
1
©2014 Integrated Devi
ce Techno
logy, Inc.
ICS8714004I Data Sheet
FemtoCLock
®
Zero Delay Buffer/Cloc
k Generator for PCI Express™ a
nd Ethernet
Typical Phase Noise at 100MHz
Noise P
ower
dBc
Hz
Offset F
requency
(Hz)
ICS8714004DKI REVISION A MARCH 24, 2014
1
2
©2014 Integrated Devi
ce Techno
logy, Inc.
ICS8714004I Data Sheet
FemtoCLock
®
Zero Delay Buffer/Cloc
k Generator for PCI Express™ a
nd Ethernet
Parameter Measurement Information
3.3V HCSL Output Load T
est Circuit
3.3V M-L
VDS Output Load T
est Circu
it
Output Ske
w
3.3V HCSL Output L
oad T
est Circuit
Differen
tial Input Le
vel
Cycl
e-to-Cyc
le Jitter
Measurement
P
oint
Measurement
P
oint
GND
2pF
2pF
0V
IREF
0V
V
DDA
V
DD
3.3V±5%
This load conditi
on is used for V
MAX
, V
MIN,
V
RB,
t
ST
ABLE,
V
CROSS,
V
CROSS
and Rise/F
all Edge Rate me
asurements.
3.3V±5%
SCOPE
Qx
nQx
3.3V±5%
POWER SUPPL
Y
+–
Float GND
V
DDA
V
DD
nQx
Qx
nQy
Qy
This load condition is used for I
DD
,
tjit(cc), tjit
(Ø) and tsk(o)
measurements.
3.3V±5
%
V
DDA
V
DD
3.3V±5%
V
CMR
Cross Points
V
PP
V
DD
GND
nCLK
CLK
Q0:Q3,
FBOUT
nQ0:Q3,
nFBOUT
t
cycle n
t
cycle n+1
t
jit(cc) =
|
t
cycle n –
t
cycle n+1
|
1000 Cycles
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P31
8714004DKILF
Mfr. #:
Buy 8714004DKILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products FemtoClock Zero Delay Buffer PCIe
Lifecycle:
New from this manufacturer.
Delivery:
DHL
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TNT
EMS
Payment:
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8714004DKILF