8714004DKILF Datasheet 8714004DKILF | P16-P18

ICS8714004I Data Sheet FemtoCLock

Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet

floating (FBO_DIV and FBI_DIV1:0). QDIV0 needs to be ÷4, which

is a default value so this pin can be left floating. QDIV1 must be HIGH

for ÷5, so this pin must be pulled high or driven high externally.

OE[1:0] = 01, so OE0 can Float and OE1 must be pulled Low.

Figure 1, Example Backplane Application

Bold lines indicate active clock path

This example shows a case where each card may be dynamically

configured as a master or slave card, hence the need for an

ICS8714004I and ICS841402I on each card. On the master timing

card, the ICS841402I provides a 100MHz reference to the

ICS8714004I CLK, nCLK input. The M-LVDS pair on the

ICS8714004I is configured as an output (OE_MLVDS = Logic 1) and

the internal divider is set to ÷4 to generate 25MHz M-LVDS to the

backplane. The 25MHz clock is also used as a reference to the

FemtoClock PLL which multiplies to a VCO frequency of 500MHz.

Each of the four output pairs may be individually set for ÷4 or ÷5 for

125MHz or 100MHz operation respectively and in this example, one

output pair is set to 100MHz for the FPGA and another output pair is

set to 125MHz for the PCI Express serdes. For the slave card, the

M-LVDS pair is configured as an input (OE_MLVDS = LOW) and the

FemtoClock PLL multiplies this reference frequency to 500MHz VCO

frequency and the output dividers are set to provide 100MHz to the

FPGA and 125MHz to the PCI Express Serdes as shown.

SSC Synthesizer

ICS841402I

100 MHz HCSL

ICS8714004I

÷4

FemtoClock

VCO

100 MHz HCSL

125 MHz HCSL

FPGA

PCIe Serdes

25 MHz

SSC Synthesizer

ICS841402I

ICS8714004I

÷4

FemtoClock

VCO

100 MHz HCSL

125 MHz HCSL

FPGA

PCIe Serdes

25 MHz

MLVDS

Master Clock Card

Slave Clock Card

Backplane

Slave synthesizer

Off or output disabled

CLK

MLVDS

CLK

ICS8714004I Data Sheet FemtoCLock

Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how a differential input can be wired to accept single

ended levels. The reference voltage V

= V

/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need

to be adjusted to position the V

in the center of the input voltage

swing. For example, if the input clock swing is 3.3V and V

= 3.3V,

R1 and R2 value should be adjusted to set V

at 1.25V. The values

below are for when both the single ended swing and V

are at the

same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V

cannot be less

than -0.3V and V

cannot be more than V

+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

ICS8714004I Data Sheet FemtoCLock

Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by one

side of a differential driver through an AC coupling capacitor. The

XTAL_OUT pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 3A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50

 applications,

R1 and R2 can be 100

. This can also be accomplished by removing

R1 and changing R2 to 50. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 3B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the XTAL_IN input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a quartz crystal as the input.

Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface

VCC

XTAL_OUT

XTAL_IN

100

Zo = 50 ohmsRs

Zo = Ro + Rs

.1uf

LVCMOS Driver

XTA L_O U T

XTA L_I N

Zo = 50 ohms

.1uf

LVPECL Driver

Zo = 50 ohms

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8714004DKILF

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