IDT and IDT logo are trademarks of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-6777/2
1 November 14, 2012
T1/E1/OC3 TELECOM CLOCK GENERATOR
WITH DUAL REFERENCE INPUTS
IDT82V3010
FEATURES
Supports AT&T TR62411
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz
Accepts two independent reference inputs which may have
same or different nominal frequencies applied to them
Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o
output clock signals
Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,
F32o, RSP and TSP
Provides a C2/C1.5 output clock signal with the frequency
controlled by the selected reference input Fref0 or Fref1
Phase slope of 5 ns per 125 µs
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
•MTIE of 1 µs
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input reference quality indication
3.3 V operation with 5 V tolerant I/O
Package: 56-pin SSOP (Green option available)
FUNCTIONAL BLOCK DIAGRAM
OSC
Reference Input
Switch
TIE Control
Block
Reference Input
Monitor 0
OSCi TCLR V
DDD
V
SS
V
SS
C16o
C8o
C4o
C2o
C3o
C1.5o
F0o
F8o
F16o
RSP
TSP
F0_sel0
F0_sel1
FreerunNormal Holdover
TDO TDI
MON_out0
Fref1
Fref0
IN_sel
Virtual
Reference
FLOCK
Invalid Input
Signal Detection
F19o
C6o
JTAG
LOCK
MODE_sel0MODE_sel1TIE_en
TMS
TRST
TCK
V
DDD
V
SS
V
DDD
V
DDA
V
SS
RST
F32o
Feedback Signal
State Control Circuit
Reference Input
Monitor 1
MON_out1
C19POS
C19NEG
Frequency
Select Circuit 0
Frequency
Select Circuit 1
F1_sel0
F1_sel1
C32o
C19o
DPLL
C2/C1.5
V
DDA
V
SS
IDT82V3010 T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs
Description 2 November 14, 2012
DESCRIPTION
The IDT82V3010 is a T1/E1/OC3 telecom clock generator with dual
reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which
generates low jitter ST-BUS and 19.44 MHz clock and framing signals
that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
input reference.
The IDT82V3010 provides 9 types of clock signals (C1.5o, C3o, C6o,
C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o,
F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3
links.
The IDT82V3010 is compliant with AT&T TR62411 and ETSI ETS
300 011. It meets the jitter/wander tolerance, jitter/wander transfer,
intrinsic jitter/wander, frequency accuracy, capture range, phase change
slope, holdover frequency accuracy and MTIE (Maximum Time Interval
Error) requirements for these specifications.
The IDT82V3010 can be used in synchronization and timing control
for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse
source. It also can be used in access switch, access routers, ATM edge
switches, wireless base station controllers, or IADs (Integrated Access
Devices), PBXs, line cards and SONET/SDH equipments.
PIN CONFIGURATION
Figure - 1 IDT82V3010 SSOP56 Package Pin Assignment
IDT82V3010
14
15
16
17
18
19
20
21
22
23
24
RST
MON_out0
Fref1
Fref0
F19o
OSCi
F8o
C1.5o
LOCK
C2o
C4o
FLOCK
F0_sel1
F0_sel0
C3o
C8o
C16o
C32o
F0o
F16o
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
RSP
TSP
C6o
V
DDD
TDI
TMS
TRST
TDOTCK
IC0
HOLDOVER
FREERUN
NORMAL
TIE_en
V
DDD
VSS
VSS
C19o
MODE_sel0
MODE_sel1
TCLR
IN_sel
25
26
27
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
28
29
V
DDD
VSS
VDDA
VSS
F32o
V
SS
VDDA
C2/C1.5
IC2
F1_sel0
F1_sel1
C19NEG
C19POS
MON_out1
IDT82V3010 T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs
Table Of Contents 3 November 14, 2012
TABLE OF CONTENTS
1 Pin Description...................................................................................................................................................................................................7
2 Functional Description......................................................................................................................................................................................9
2.1 State Control Circuit ..................................................................................................................................................................................9
2.1.1 Normal Mode..............................................................................................................................................................................10
2.1.2 Fast Lock Mode..........................................................................................................................................................................10
2.1.3 Holdover Mode...........................................................................................................................................................................10
2.1.4 Freerun Mode.............................................................................................................................................................................10
2.2 Frequency Select Circuit .........................................................................................................................................................................10
2.3 Reference Input Switch ...........................................................................................................................................................................10
2.4 Reference Input Monitor..........................................................................................................................................................................11
2.5 Invalid Input Signal Detection..................................................................................................................................................................11
2.6 TIE Control Block.....................................................................................................................................................................................11
2.7 DPLL Block..............................................................................................................................................................................................12
2.7.1 Phase Detector (PHD)................................................................................................................................................................12
2.7.2 Limiter.........................................................................................................................................................................................12
2.7.3 Loop Filter ..................................................................................................................................................................................13
2.7.4 Fraction Block.............................................................................................................................................................................13
2.7.5 Digital Control Oscillator (DCO)..................................................................................................................................................13
2.7.6 Lock Indicator.............................................................................................................................................................................13
2.7.7 Output Interface..........................................................................................................................................................................13
2.8 OSC.........................................................................................................................................................................................................14
2.8.1 Clock Oscillator ..........................................................................................................................................................................14
2.9 JTAG .......................................................................................................................................................................................................14
2.10 Reset, Lock and TIE Application .............................................................................................................................................................14
2.11 Power Supply Filtering Techniques.........................................................................................................................................................15
3 Measures of Performance...............................................................................................................................................................................16
3.1 Intrinsic Jitter ...........................................................................................................................................................................................16
3.2 Jitter Tolerance........................................................................................................................................................................................16
3.3 Jitter Transfer ..........................................................................................................................................................................................16
3.4 Frequency Accuracy................................................................................................................................................................................16
3.5 Holdover Accuracy ..................................................................................................................................................................................16
3.6 Capture Range ........................................................................................................................................................................................16
3.7 Lock Range .............................................................................................................................................................................................16
3.8 Phase Slope............................................................................................................................................................................................16
3.9 Time Interval Error (TIE)..........................................................................................................................................................................16
3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................16
3.11 Phase Continuity .....................................................................................................................................................................................16
3.12 Phase Lock Time.....................................................................................................................................................................................17
4 Absolute Maximum Ratings............................................................................................................................................................................18
5 Recommended DC Operating Conditions .....................................................................................................................................................18
6 DC Electrical Characteristics..........................................................................................................................................................................18
6.1 Single End Input/Output Port...................................................................................................................................................................18
6.2 Differential Output Port (LVDS) ...............................................................................................................................................................19
7 AC Electrical Characteristics..........................................................................................................................................................................20
7.1 Performance............................................................................................................................................................................................20
7.2 Intrinsic Jitter Unfiltered...........................................................................................................................................................................20
7.3 C1.5o (1.544 MHz) Intrinsic Jitter Filtered...............................................................................................................................................21
7.4 C2o (2.048 MHz) Intrinsic Jitter Filtered..................................................................................................................................................21
7.5 C19o (19.44 MHz) Intrinsic Jitter Filtered................................................................................................................................................21
7.6 8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................21
7.7 1.544 MHz Input to 1.544 MHz Output Jitter Transfer.........................................................................
....................................................22
7.8 2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................22

82V3010PVG

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products T1/E1/OC3 WAN PLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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