82V3010PVG Datasheet 82V3010PVG, 82V3010PVG8 | P4-P6

IDT82V3010 T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs

Table Of Contents 4 November 14, 2012

7.9 19.44 MHz Input to 19.44 MHz Output Jitter Transfer.............................................................................................................................22

7.10 8 kHz Input Jitter Tolerance.....................................................................................................................................................................23

7.11 1.544 MHz Input Jitter Tolerance ............................................................................................................................................................23

7.12 2.048 MHz Input Jitter Tolerance ............................................................................................................................................................23

7.13 19.44 MHz Input Jitter Tolerance ............................................................................................................................................................24

8 Timing Characteristics ....................................................................................................................................................................................26

8.1 Timing Parameter Measurement Voltage Levels ....................................................................................................................................26

8.2 Input/Output Timing.................................................................................................................................................................................26

9 Ordering Information.......................................................................................................................................................................................31

IDT82V3010 T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs

List of Figures 5 November 14, 2012

LIST OF FIGURES

Figure - 1 IDT82V3010 SSOP56 Package Pin Assignment................................................................................................................................ 2

Figure - 2 State Control Circuit............................................................................................................................................................................ 9

Figure - 3 State Control Diagram......................................................................................................................................................................... 9

Figure - 4 TIE Control Block Diagram................................................................................................................................................................ 11

Figure - 5 Reference Switch with TIE Control Block Enabled............................................................................................................................ 12

Figure - 6 Reference Switch with TIE Control Block Disabled........................................................................................................................... 12

Figure - 7 DPLL Block Diagram......................................................................................................................................................................... 13

Figure - 8 Clock Oscillator Circuit...................................................................................................................................................................... 14

Figure - 9 Power-Up Reset Circuit..................................................................................................................................................................... 14

Figure - 10 IDT82V3010 Power Decoupling Scheme.......................................................................................................................................... 15

Figure - 11 Timing Parameter Measurement Voltage Levels.............................................................................................................................. 26

Figure - 12 Input to Output Timing (Normal Mode).............................................................................................................................................. 28

Figure - 13 Output Timing 1................................................................................................................................................................................. 29

Figure - 14 Output Timing 2................................................................................................................................................................................. 30

Figure - 15 Input Control Setup and Hold Timing................................................................................................................................................ 30

IDT82V3010 T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs

List of Tables 6 November 14, 2012

LIST OF TABLES

Table - 1 Operating Modes Selection..................................................................................................................................................................9

Table - 2 Fref0 Frequency Selection.................................................................................................................................................................10

Table - 3 Fref1 Frequency Selection.................................................................................................................................................................10

Table - 4 Input Reference Selection..................................................................................................................................................................11

Table - 5 C2/C1.5 Output Frequency Control....................................................................................................................................................14

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

82V3010PVG

Mfr. #:

Buy 82V3010PVG

Manufacturer:

IDT

Description:

Clock Generators & Support Products T1/E1/OC3 WAN PLL

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

82V3010PVG

82V3010PVG

Products related to this Datasheet