IDT82V3010 T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs
Pin Description 7 November 14, 2012
1 PIN DESCRIPTION
Name Type Pin Number Description
V
SS
Power
12, 18, 27
38, 47
Ground.
0 V. All V
SS
pins should be connected to the ground.
V
DDD
Power 13, 19, 26
3.3 V Digital Power Supply.
Refer to “2.11 Power Supply Filtering Techniques”.
V
DDA
Power 37, 48
3.3 V Analog Power Supply.
Refer to “2.11 Power Supply Filtering Techniques”.
OSCi (CMOS) I 50
Oscillator Master Clock Input.
This pin is connected to a clock source.
Fref0
Fref1
I
5
6
Reference Input 0 and Reference Input 1.
These are two input reference sources (falling edge of 8 kHz, 1.544 MHz and 2.048 MHz or rising edge of 19.44
MHz) used for synchronization. The IN_sel pin determines which one of the two reference inputs to be used. See
Table - 4 for details.
The frequency of the reference inputs can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. These two pins are
internally pulled up to V
DDD
.
IN_sel I11
Input Reference Selection.
A logic low at this pin selects Reference Input 0 (Fref0) and a logic high at this pin selects Reference Input 1 (Fref1).
The logic level on this input is gated in by the rising edges of F8o. This Pin is internally pulled down to V
SS
.
F0_sel0
F0_sel1
I
9
10
Frequency Selection Inputs for Fref0.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 0 (Fref0). See Table - 2 for details.
F1_sel0
F1_sel1
I
35
34
Frequency Selection Inputs for Fref1.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 1 (Fref1). These two pins are internally pulled down to V
ss
. See Table - 3 for details.
MODE_sel0
MODE_sel1
I
1
2
Mode Selection Inputs.
These two inputs determine the operating mode of the IDT82V3010 (Normal, Holdover or Freerun). See Table - 1 for
details.
The logic levels on these two pins are gated in by the rising edges of F8o. These two pins are internally pulled down
to V
SS
.
RST I4
Reset Input.
Pulling this pin to logic low for at least 300 ns will reset the IDT82V3010. While the RST pin is low, all framing and
clock outputs are at logic high.
To ensure proper operation, the device must be reset after it is powered up.
TCLR I3
TIE Control Block Reset.
Pulling this pin to logic low for at least 300 ns will reset the TIE (Maximum Time Interval Error) control block and
result in a realignment of the output phase with the input phase. This pin is internally pulled up to V
DDD
.
TIE_en I56
TIE Control Block Enable.
A logic high at this pin enables the TIE control block while a logic low disables it. The logic level on this input is gated
in by the rising edges of F8o. This pin is internally pulled down to V
ss
.
FLOCK I45
Fast Lock Mode Enable.
When this pin is set to logic high, the DPLL will quickly lock to the input reference within 500 ms.
LOCK (CMOS) O 44
Lock Indicator.
This output pin will go high when the DPLL is frequency locked to the input reference.
HOLDOVER (CMOS) O 52
Holdover Indicator.
This output pin will go high whenever the DPLL enters Holdover mode.
NORMAL (CMOS) O 46
Normal Indicator.
This output pin will go high whenever the DPLL enters Normal mode.
FREERUN (CMOS) O 51
Freerun Indicator.
This output pin will go high whenever the DPLL enters Freerun mode.
MON_out0 O 7
Frequency Out-of-range Indicator for Fref0.
A logic high at this pin indicates that Fref0 is off the nominal frequency by more than ±12 ppm.
MON_out1 O 8
Frequency Out-of-range Indicator for Fref1.
A logic high at this pin indicates that Fref1 is off the nominal frequency by more than ±12 ppm.
C19POS
C19NEG
(LVDS) O
21
22
19.44 MHz Clock Output (LVDS Level).
This pair of outputs is used for OC3/STS3 applications.
