NCV8871
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10
UVLO
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
To avoid any lock state under UVLO conditions, the
EN/SYNC pin should be in logic−low state. For further
details, please refer to EN/SYNC paragraph.
Internal Soft−Start
To insure moderate inrush current and reduce output
overshoot, the NCV8871 features a soft start which charges a
capacitor with a fixed current to ramp up the reference voltage.
This fixed current is based on the switching frequency, so
that if the NCV8871 is synchronized to twice the default
switching frequency the soft start will last half as long.
VDRV
An internal regulator provides the drive voltage for the
gate driver. Bypass with a ceramic capacitor to ground to
ensure fast turn on times. The capacitor should be between
0.1 mF and 1 mF, depending on switching speed and charge
requirements of the external MOSFET.
GDRV
An R
GND
= 15 kW (typical) GDRV−GND resistor is
strongly recommended.
APPLICATION INFORMATION
Design Methodology
This section details an overview of the component selection
process for the NCV8871 in continuous conduction mode
boost. It is intended to assist with the design process but does
not remove all engineering design work. Many of the
equations make heavy use of the small ripple approximation.
This process entails the following steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select Output Inductor
4. Select Output Capacitors
5. Select Input Capacitors
6. Select Feedback Resistors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
10. Determine Feedback Loop Compensation Network
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
V
IN(min)
: minimum input voltage [V]
V
IN(max):
maximum input voltage [V]
V
OUT
: output voltage [V]
I
OUT(max)
: maximum output current [A]
I
CL
: desired typical cycle-by-cycle current limit [A]
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
D
min
+ 1 *
V
IN(max)
V
OUT
D
max
+ 1 *
V
IN(min)
V
OUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be negative. This is because a boost converter
cannot have an output lower than the input. In situations
where the input is higher than the output, the output will
follow the input, minus the diode drop of the output diode
and the converter will not attempt to switch.
If the calculated D
max
is higher the D
max
of the NCV8871,
the conversion will not be possible. It is important for a boost
converter to have a restricted D
max
, because while the ideal
conversion ration of a boost converter goes up to infinity as
D approaches 1, a real converters conversion ratio starts to
decrease as losses overtake the increased power transfer. If
the converter is in this range it will not be able to regulate
properly.
If the following equation is not satisfied, the device will
skip pulses at high V
IN
:
D
min
f
s
w t
on(min)
Where: f
s
: switching frequency [Hz]
t
on(min)
: minimum on time [s]
2. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor from the source of the MOSFET to device ground.
The sense resistor should be selected as follows:
R
S
+
V
CL
I
CL
Where: R
S
: sense resistor [W]
V
CL
: current limit threshold voltage [V]
I
CL
: desire current limit [A]
3. Select Output Inductor
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case V
IN
, but
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11
operation should be verified empirically. The worst case V
IN
is half of V
OUT
, or whatever V
IN
is closest to half of V
OUT
.
After choosing a peak current ripple value, calculate the
inductor value as follows:
L +
V
IN(WC)
D
WC
DI
L,max
f
s
Where: V
IN(WC)
: V
IN
value as close as possible to
half of V
OUT
[V]
D
WC
: duty cycle at V
IN(WC)
DI
L,max
: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated
as follows:
I
L,AVG
+
V
OUT
I
OUT(max)
V
IN(min)
h
The Peak Inductor current can be calculated as follows:
I
L,peak
+ I
L,avg
)
DI
L,max
2
Where: I
L,peak
: Peak inductor current value [A]
4. Select Output Capacitors
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
V
OUT(ripple)
+
DI
OUT(max)
fC
OUT
)
ǒ
I
OUT(max)
1 * D
)
V
IN(min)
D
2fL
Ǔ
R
ESR
The capacitors need to survive an RMS ripple current as
follows:
I
Cout(RMS)
+ I
OUT
D
WC
DȀ
WC
)
D
WC
12
ǒ
DȀ
WC
L
R
OUT
T
SW
Ǔ
2
Ǹ
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
5. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
I
Cin(RMS)
+
V
IN(min)
2
D
WC
Lf
s
V
OUT
23
Ǹ
6. Select Feedback Resistors
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
pin. During regulation, the divided voltage will equal V
ref
.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
R
upper
+ R
lower
ǒ
V
out
* V
ref
Ǔ
V
ref
The total feedback resistance (R
upper
+ R
lower
) should be in
the range of 1 kW – 100 kW.
7. Select Compensator Components
Current Mode control method employed by the NCV8871
allows the use of a simple, Type II compensation to optimize
the dynamic response according to system requirements.
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
Q
g(total)
v
I
drv
f
s
Where: Q
g(total)
: Total Gate Charge of MOSFET(s) [C]
I
drv
: Drive voltage current [A]
f
s
: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
I
Q(max)
+ I
out
D
Ǹ
DȀ
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
V
Q(max)
+ V
OUT(max)
9. Select Diode
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
I
D(avg)
+ I
OUT(max)
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
V
D(max)
+ V
OUT(max)
The maximum power dissipation in the diode can be
calculated as follows:
P
D
+ V
f(max)
I
OUT(max)
Where: P
d
: Power dissipation in the diode [W]
V
f(max)
: Maximum forward voltage of the diode [V]
10. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(R
ESD
502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (V
CTRL
) may differ from the
IC-VC signal if R
2
is of similar order of magnitude as R
ESD
.
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12
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type-I compensation is not possible due to the presence
of R
ESD
. The Figures 12 and 13 compensation networks
correspond to a Type-II network in series with R
ESD
.
The resulting control-output transfer function is an accurate
mathematical model of the IC in a boost converter topology.
The model does have limitations and a more accurate SPICE
model should be considered for a more detailed analysis:
The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
The CCM Boost control-output transfer function
includes operating efficiency as a correction factor to
improve modeling accuracy under low input voltage
and high output current operating conditions where
operating losses becomes significant.
Rds(on)
V
d
L
GND
ISNS
VFB
GDRV
VC
R
i
C
OUT
V
OUT
C
1
R
2
V
CTRL
OTA
V
IN
r
L
r
Cf
C
2
R
OUT
R
ESD
R
0
R
1
R
low
Figure 12. NCV8871 Boost Converter OTA and Compensation

NCV887103D1R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers AUTOMOTIVE-GRADE NON-SYNC
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