Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. C
03/21/2008
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS61C25616AL IS61C25616AS
IS64C25616AL IS64C25616AS
FEATURES
HIGH SPEED: (IS61/64C25616AL)
• High-speed access time: 10ns, 12 ns
• Low Active Power: 150 mW (typical)
• Low Standby Power: 10 mW (typical)
CMOS standby
LOW POWER: (IS61/64C25616AS)
• High-speed access time: 25 ns
• Low Active Power: 75 mW (typical)
• Low Standby Power: 1 mW (typical)
CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Available in 44-pin SOJ package and
44-pin TSOP (Type II)
• Commercial, Industrial and Automotive tempera-
ture ranges available
• Lead-free available
DESCRIPTION
The ISSI IS61C25616AL/AS and IS64C25616AL/AS are
high-speed, 4,194,304-bit static RAMs organized as 262,144
words by 16 bits. They are fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61C25616AL/AS and IS64C25616AL/AS are pack-
aged in the JEDEC standard 44-pin 400-mil SOJ and 44-pin
TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
MARCH 2008
A0-A17
CE
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
256K x 16 HIGH-SPEED CMOS STATIC RAM
