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NCP1606BDR2G

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NCP1606
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10
a high frequency switching converter which regulates the
input current to stay in phase with the input voltage. These
circuits operate at a higher frequency and so they are
smaller, lighter in weight, and more efficient than a passive
circuit. With proper control of an active PFC stage, almost
any complex load can be made to appear in phase with the
ac line, thus significantly reducing the harmonic current
content. Because of these advantages, active PFC circuits
have become the most popular way to meet harmonic
content requirements. Generally, they consist of inserting
a PFC pre−regulator between the rectifier bridge and the
bulk capacitor (Figure 22).
Figure 22. Active PFC Pre−Converter with the NCP1606
Rectifiers
+
AC Line
High
Frequency
Bypass
Capacitor
NCP1606
PFC Preconverter
Converter
Load
+
Bulk
Storage
Capacitor
The boost (or step up) converter is the most popular
topology for active power factor correction. With the
proper control, it produces a constant voltage while
drawing a sinusoidal current from the line. For medium
power (<300 W) applications, critical conduction mode
(also called borderline conduction mode) is the preferred
control method. Critical conduction mode (CRM) occurs at
the boundary between discontinuous conduction mode
(DCM) and continuous conduction mode (CCM). In CRM,
the next driver on time is initiated when the boost inductor
current reaches zero. CRM operation is an ideal choice for
medium power PFC boost stages because it combines the
lower peak currents of CCM operation with the zero current
switching of DCM operation. The operation and
waveforms in a PFC boost converter are illustrated in
Figure 23.
Figure 23. Schematic and Waveforms of an Ideal CRM Boost Converter
Diode Bridge
IN
+
−
L
Diode Bridge
IN
+
−
L
+
The power switch is ON The power switch is OFF
Critical Conduction Mode:
Next current cycle starts as
soon as the core is reset.
Coil
Current
+
The power switch being about zero, the input voltage
is applied across the coil. The coil current linearly
increases with a (V
in
/L) slope.
The coil current flows through the diode. The coil voltage is (V
OUT
−
V
in
) and the coil current linearly decays with a (V
OUT
− V
in
)/L slope.
I
coil
V
OUT
V
in
V
d
(V
OUT
− V
in
)/L
I
coil_pk
I
coil
V
in
V
d
V
d
V
in
/L
V
OUT
V
in
If next cycle does not start
then V
d
rings towards V
in
+
NCP1606
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11
When the switch is closed, the inductor current increases
linearly to its peak value. When the switch opens, the
inductor current linearly decreases to zero. At this point,
the drain voltage of the switch (V
d
) is essentially floating
and begins to drop. If the next switching cycle does not
start, then the voltage will ring with a dampened frequency
around V
in
. A simple derivation of equations (such as found
in AND8123), leads to the result that good power factor
correction in CRM operation is achieved when the on time
is constant across an ac cycle and is equal to:
t
on
+
2 @ P
OUT
@ L
h @ Vac
RMS
2
(eq. 1)
A simple plot of this switching over an ac line cycle is
illustrated in Figure 24. The off time varies based on the
instantaneous line voltage, but the on time is kept constant.
This naturally causes the peak inductor current (I
Lpk
) to
follow the ac line voltage.
The NCP1606 represents an ideal method to implement
this constant on time CRM control in a cost effective and
robust solution. The device incorporates an accurate
regulation circuit, a low power startup circuit, and
advanced protection features.
Figure 24. Inductor Waveform During CRM Operation
ON
OFF
MOSFET
I
in
(t)
I
L
(t)
V
in
(t)
V
inpk
I
Lpk
I
inpk
ERROR AMPLIFIER REGULATION
The NCP1606 is configured to regulate the boost output
voltage based on its built in error amplifier (EA). The error
amplifier ’s negative terminal is pinned out to FB, the
positive terminal is tied to a 2.5 V ± 1.6% reference, and the
output is pinned out to Control (Figure 25).
Figure 25. Error Amplifier and On Time Regulation Circuits
FB
Control
+
−
EA
+
2.5 V
PWM BLOCK
V
CONTROL
R
OUT2
R
OUT1
C
COMP
t
PWM
t
ON(max)
V
OUT
t
ON
V
EAL
V
EAH
Slope +
Ct
I
CHARGE
V
CONTROL
A resistor divider from the boost output to the input of the
EA sets the FB level. If the output voltage is too low, then
the FB level will drop and the EA will cause the control
voltage to increase. This increases the on time of the driver,
which increases the power delivered and brings the output
back into regulation. Alternatively, if the output voltage
(and hence FB voltage) is too high, then the control level
decreases and the driver on times are shortened. In this way,
the circuit regulates the output voltage (V
OUT
) so that the
V
OUT
portion that is applied to FB through the resistor
divider R
OUT1
and R
OUT2
is equal to the internal reference
(2.5 V). The output voltage can then be easily set according
to the following equation:
V
OUT
+ 2.5 V @
R
OUT1
) R
OUT2
R
OUT2
(eq. 2)
A compensation network is placed between the FB and
Control pins to reduce the speed at which the EA responds
to changes in the boost output. This is necessary due to the
nature of an active PFC circuit. The PFC stage absorbs a
sinusoidal current from a sinusoidal line voltage. Hence,
the converter provides the load with a power that matches
NCP1606
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12
the average demand only. Therefore, the output capacitor
must “absorb” the difference between the delivered power
and the power consumed by the load. This means that when
the power fed to the load is lower than the demand, the
output capacitor discharges to compensate for the lack of
power. Alternatively, when the supplied power is higher
than that absorbed by the load, the output capacitor charges
to store the excess energy. The situation is depicted in
Figure 26.
Figure 26. Output Voltage Ripple for a Constant Output Power
V
OUT
P
OUT
P
IN
Iac
Vac
As a consequence, the output voltage exhibits a ripple at
a frequency of either 100 Hz (for 50 Hz mains such as in
Europe) or 120 Hz (for 60 Hz mains in the USA). This
ripple must not be taken into account by the regulation loop
because the error amplifier’s output voltage must be kept
constant over a given ac line cycle for a proper shaping of
the line current. Due to this constraint, the regulation
bandwidth is typically set below 20 Hz. For a simple type 1
compensation network, only a capacitor is placed between
FB and Control (see Figure 1). In this configuration, the
capacitor necessary to attenuate the bulk voltage ripple is
given by:
C
COMP
+
10
G
20
4 @ p f
line
@ R
OUT1
(eq. 3)
where G is the attenuation level in dB (commonly 60 dB)
ON TIME SEQUENCE
Since the NCP1606 is designed to control a CRM boost
converter, its switching pattern must accommodate
constant on times and variable off times. The Controller
generates the on time via an external capacitor connected
to pin 3 (Ct). A current source charges this capacitor to a
level determined by the Control pin voltage. Specifically,
Ct is charged to V
CONTROL
minus the V
EAL
offset
(typically 2.1 V). Once this level is exceeded, the drive is
turned off (Figure 27).
Figure 27. On Time Generation
Control
Ct
+
−
PWM
+
DRV
I
CHARGE
t
ON
V
EAL
V
CONTROL
− V
EAL
t
ON
V
Ct
V
Ct(off)
V
DD
DRV
V
CONTROL
Since V
CONTROL
varies with the RMS line level and
output load, this naturally satisfies equation 1. And if the
values of compensation components are sufficient to filter
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NCP1606BDR2G

Mfr. #:
Buy NCP1606BDR2G
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC PWR FCTR CONTROLLER
Lifecycle:
New from this manufacturer.
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