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13
out the bulk voltage ripple, then this on time is truly
constant over the ac line cycle.
Note that the maximum on time of the controller occurs
when V
CONTROL
is at its maximum. Therefore, the Ct
capacitor must be sized to ensure that the required on time
can be delivered at full power and the lowest input voltage
condition. The maximum on time is given by:
t
ON(max)
+
Ct @ V
CTMAX
I
CHARGE
(eq. 4)
Combining this equation with equation 1, gives:
Ct w
2 @ P
OUT
@ L @ I
CHARGE
h @ Vac
RMS
2
@ V
CTMAX
(eq. 5)
where V
CTMAX
= 2.9 V (min)
I
CHARGE
= 297 mA (max)
OFF TIME SEQUENCE
While the on time is constant across the ac cycle, the off
time in CRM operation varies with the instantaneous input
voltage. The NCP1606 determines the correct off time by
sensing the inductor voltage. When the inductor current
drops to zero, the drain voltage (“Vd” in Figure 23) is
essentially floating and naturally begins to drop. If the
switch is turned on at this moment, then CRM operation
will be achieved. To measure this high voltage directly on
the inductor is generally not economical or practical.
Rather, a smaller winding is taken off of the boost inductor.
This winding, called the zero current detector (ZCD)
winding, gives a scaled version of the inductor output and
is more useful to the controller.
Figure 28. Voltage Waveforms for Zero Current
Detection
DRIVE
Winding
Pin
Drain
0.6 V
V
OUT
5.7 V
2.1 V
1.6 V
ZCD
Figure 28 gives typical operating waveforms with the
ZCD winding. When the drive is on, a negative voltage
appears on the ZCD winding. And when the drive is off, a
positive voltage appears. When the inductor current drops
to zero, then the ZCD voltage falls and starts to ring around
zero volts. The NCP1606 detects this falling edge and starts
the next driver on time. To ensure that a ZCD event has
truly occurred, the NCP1606’s logic (Figure 29) waits for
the ZCD pin voltage to rise above V
ZCDH
(2.1 V typical)
and then fall below V
ZCDL
(1.6 V typical). In this way,
CRM operation is easily achieved.
Figure 29. Implementation of the ZCD Winding
ZCD
+
+
200 mV
+
+
2.1 v
VCL(POS)
Clamp
Shutdown
Demag
VCL(NEG)
Active
Clamp
+
+
1.6 V
Reset
Dominant
Latch
R
QS
DRIVE
R
SENSE
R
ZCD
V
DD
V
in
N
ZCD
Q
N
B
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14
To prevent negative voltages on the ZCD pin, the pin is
internally clamped to V
CL(NEG)
(600 mV typ) when the
ZCD winding is negative. Similarly, the ZCD pin is
clamped to V
CL(POS)
(5.7 V typical), when the voltage rises
too high. Because of these clamps, a resistor (R
ZCD
in
Figure 29) is necessary to limit the current from the ZCD
winding to the ZCD pin.
At startup, there is no energy in the ZCD winding and
therefore no voltage signal to activate the ZCD
comparators. This means that the driver could never turn
on. Therefore, to enable the PFC stage to startup under
these conditions, an internal watchdog timer is integrated
into the controller. This timer turns the drive on if the driver
has been off for more than 180 ms (typical). Obviously, this
feature is deactivated during a fault mode (OVP, UVP, or
Shutdown), and reactivated when the fault is removed.
STARTUP
Generally, a resistor connected between the ac input and
V
CC
(pin 8) charges the V
CC
capacitor to the V
CC(on)
level
(12 V typical). Because of the very low consumption of the
NCP1606 during this stage (< 40 mA), most of the current
goes directly to charging up the V
CC
capacitor. This
provides faster startup times and reduced standby power
dissipation. When the V
CC
voltage exceeds the V
CC(on)
level, the internal references and logic of the NCP1606 turn
on. The controller has an undervoltage lockout (UVLO)
feature which keeps the part active until V
CC
drops below
V
CC(off)
(9.5 V typical). This hysteresis allows ample time
for the auxiliary winding to take over and supply the
necessary power to V
CC
(Figure 30).
Figure 30. Typical V
CC
Startup Waveform
V
CC
V
CC(on)
V
CC(off)
When the PFC preconverter is loaded by a switch mode
power supply (SMPS), then it is often preferable to have the
SMPS controller startup first. The SMPS can then supply
the NCP1606 V
CC
directly. Advanced controllers, such as
the NCP1230 or NCP1381, can control when to turn on the
PFC stage (see Figure 31) leading to optimal system
performance. This setup also eliminates the startup
resistors and therefore improves the no load power
dissipation of the system.
Figure 31. NCP1606 Supplied by a Downstream SMPS Controller (NCP1230)
1
7
6
5
2
3
4
NCP1606
+
+
+
+
1
7
6
5
2
3
4
NCP1230
PFC_Vcc
88
V
CC
+
C
bulk
D
boost
QUICK START and SOFT START
At startup, the error amplifier is enabled and Control is
pulled up to V
EAL
(typically 2.1 V). This is the lowest level
of control voltage which produces output drives. This
feature, called “quick start,” eliminates the delay at startup
associated with charging the compensation network to its
minimum level. This also produces a natural “soft start”
mode where the controller’s power ramps up from zero to
the required power (see Figure 32).
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15
Figure 32. Startup Timing Diagram Showing the
Natural Soft Start of the Control
Pin
FB
Control
2.5 V
Natural Soft Start
V
CC
I
switch
V
EAL
V
OUT
V
CC(off)
V
CC(on)
OUTPUT DRIVER
The NCP1606 includes a powerful output driver capable
of peak currents of +500 mA and 800 mA. This enables
the controller to efficiently drive power MOSFETs for
medium power (up to 300 W) applications. Additionally,
the driver stage is equipped with both passive and active
pull down clamps (Figure 33). The clamps are active when
V
CC
is off and force the driver output to well below the
threshold voltage of a power MOSFET.
Figure 33. Output Driver Stage and Pull Down Clamps
UVLO
DRV
GND
+
+
DRV IN
uV
DD
V
CC
V
DD
V
ddGD
V
DD
REG
UVLO
Overvoltage Protection
The low bandwidth of the feedback network makes
active PFC stages very slow systems. One consequence of
this is the risk of huge overshoots in abrupt transient phases
(startup, load steps, etc.). For reliable operation, it is
critical that some form of overvoltage protection (OVP)
effectively prevents the output voltage from rising too
high. The NCP1606 detects these excessive V
OUT
levels
and disables the driver until the output voltage returns to
nominal levels. This keeps the output voltage within an
acceptable range. The limit is adjustable so that the
overvoltage level can be optimally set. The level must not
be so low that it is triggered by the 100 or 120 Hz ripple of
the output voltage. But it must be low enough so as not to
require a larger voltage rating of the output capacitor.
Figure 34 depicts the operation of the OVP circuitry.

NCP1606BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC PWR FCTR CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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