NCP1606
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16
Figure 34. OVP and UVP Circuit Blocks
FB
Control
+
E/A
+
Measure
+
300 mV
+
2.5 V
UVP
Fault
Dynamic OVP
V
EAH
Clamp
Static OVP is triggered
when clamp is activated.
V
EAL
Clamp
Static OVP
Enable
(Enable EA)
R
OUT2
R
OUT1
C
COMP
V
DD
I
CONTROL
> I
ovp
V
OUT
I
CONTROL
V
CONTROL
I
CONTROL
When the output voltage is in steady state, R
OUT1
and
R
OUT2
regulate the FB voltage to 2.5 V. Also, during this
equilibrium state, no current flows through the
compensation capacitor (“C
COMP
” of Figure 1). Therefore:
The R
OUT1
current is:
I
R
OUT1
+
(V
OUT
)
nom
* 2.5 V
R
OUT1
(eq. 6)
where (V
OUT
)
nom
is the nominal output voltage.
The R
OUT2
current is:
I
R
OUT2
+
2.5 V
R
OUT2
(eq. 7)
And since no current flows through C
COMP
,
I
R
OUT1
+I
R
OUT2
å
(V
OUT
)
nom
* 2.5 V
R
OUT1
+
2.5 V
R
OUT2
(eq. 8)
Under stable conditions, these equations are true.
Conversely when V
OUT
is not at its nominal level, the
output of the error amplifier sinks or sources the current
necessary to maintain 2.5 V on pin 1. In particular, in the
case of an overvoltage condition:
The error amplifier maintains 2.5 V on pin 1, and the
R
OUT2
current remains:
I
R
OUT2
+
2.5 V
R
OUT2
(eq. 9)
The R
OUT1
current is:
I
R
OUT1
+
V
OUT
2.5 V
R
OUT1
+
(V
OUT
)
nom
) DV
OUT
2.5 V
R
OUT1
(eq. 10)
where DV
OUT
is the output voltage excess.
Therefore, the error amplifier sinks:
I
R
OUT1
I
R
OUT2
+
(V
OUT
)
nom
) DV
OUT
2.5 V
R
OUT1
2.5 V
R
OUT2
(eq. 11)
The combination of Equations 2 and 11 leads to a very
simple expression of the current sunk by the error
amplifier:
I
CONTROL
+ I
R
OUT1
* I
R
OUT2
+
DV
OUT
R
OUT1
(eq. 12)
Hence, the current absorbed by pin 2 (I
CONTROL
) is
proportional to the output voltage excess. The circuit
senses this current and disables the drive (pin 7) when
I
CONTROL
exceeds I
OVP
(typically 40 mA in NCP1606A,
10.4 mA in NCP1606B). This gives the OVP threshold as:
(V
OUT
)
OVP
+ (V
OUT
)
nom
) (R
OUT1
@ I
OVP
)
By simply adjusting R
OUT1
, the OVP limit can be easily
set. Therefore, one can compute the R
OUT1
and R
OUT2
resistances using the following procedure:
1. Select R
OUT1
to set the desired overvoltage level:
R
OUT1
+
(V
OUT
)
OVP
* (V
OUT
)
nom
I
OVP
For instance if implementing the NCP1606B, and
420 V is the maximum output level and 400 V is the
nominal output level, then
R
OUT1
+
420 * 400
10.4 mA
+ 1.9 MW
2. Select R
OUT2
to adjust the regulation level:
R
OUT2
+
2.5 V @ R
OUT1
V
OUT(nom)
* 2.5 V
NCP1606
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17
For the above example, this leads to:
R
OUT2
+
2.5 V
400 V * 2.5 V
@ 1.9 MW + 12.0 kW.
STATIC OVERVOLTAGE PROTECTION
If the OVP condition lasts for a long time, it may happen
that the error amplifier output reaches its minimum level
(i.e. Control = V
EAL
). It would then not be able to sink any
current and maintain the OVP fault. Therefore, to avoid any
discontinuity in the OVP disabling effect, the circuit
incorporates a comparator which detects when the lower
level of the error amplifier is reached. This event, called
“static OVP”, disables the output drives. Once the OVP
event is over, and the output voltage has dropped to normal,
then Control
rises above the lower limit and the driver is
reenabled (Figure 35).
Figure 35. OVP Timing Diagram
Vout
Vcontrol
Icontrol
Dynamic OVP
Static OVP
IovpH
IovpL
Vout(nom)
Drive
V
EAH
V
EAL
NCP1606 Undervoltage Protection (UVP)
When the PFC stage is plugged in, the output voltage is
forced to roughly equate the peak line voltage. The
NCP1606 detects an undervoltage fault when this output
voltage is unusually low, such that the feedback voltage is
below V
UVP
(300 mV typ). In an UVP fault, the drive
output and error amplifier (EA) are disabled. The latter is
done so that the EA does not source a current which would
increase the FB voltage and prevent the UVP event from
being accurately detected. The UVP feature helps to
protect the application if something is wrong with the
power path to the bulk capacitor (i.e. the capacitor cannot
charge up) or if the controller cannot sense the bulk voltage
(i.e. the feedback loop is open).
Furthermore, the NCP1606 incorporates a novel startup
sequence which ensures that undervoltage conditions are
always detected at startup. It accomplishes this by waiting
approximately 180 ms after V
CC
reaches V
CC(on)
before
enabling the error amplifier (Figure 36). During this wait
time, it looks to see if the feedback (FB) voltage is greater
than the UVP threshold. If not, then the controller enters a
UVP fault and leaves the error amplifier disabled.
However, if the FB pin voltage increases and exceeds the
UVP level, then the controller will start the application up
normally.
Figure 36. The NCP1606’s Startup Sequence with
and without a UVP Fault
FB
Control
2.5 V
UVP
UVP Wait
UVP Wait
V
UVP
V
EAH
V
EAL
V
OUT(nom)
V
OUT
V
CC(off)
V
CC(on)
V
CC
UVP Fault is “Removed”
The voltage on the output which exits a UVP fault is
given by:
V
OUT
(UVP)
+
R
OUT1
) R
OUT2
R
OUT2
@ 300 mV
(eq. 13)
If R
OUT1
= 1.9 MW and R
OUT2
= 12.0 kW, then the V
OUT
UVP threshold is 48 V. This corresponds to an input voltage
of approximately 34 Vac.
Overcurrent Protection (OCP)
A dedicated pin on the NCP1606 senses the peak current
and limits the driver on time if this current exceeds
V
CS(limit)
. This level is 1.7 V (typ) on the NCP1606A and
0.5 V (typ) on the NCP1606B. Therefore, the maximum
peak current can be adjusted by changing R
SENSE
according
to:
I
peak
+
V
CS(limit)
R
SENSE
(eq. 14)
An internal LEB filter (Figure 37) reduces the likelihood
of switching noise falsely triggering the OCP limit. This
filter blanks out the first 250 ns (typical) of the current
sense signal. If additional filtering is necessary, a small RC
filter can be added between R
SENSE
and the CS pin.
NCP1606
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18
Figure 37. OCP Circuitry with Optional External RC
Filter
CS
+
+
OCP
LEB
DRIVE
optional
R
SENSE
V
CS(limit)
SHUTDOWN MODE
The NCP1606 allows for two methods to place the
controller into a standby mode of operation. The FB pin can
be pulled below the UVP level (0.3 V typical) or the ZCD
pin can be pulled below the V
SDL
level (typically 200 mV).
If the FB pin is used for shutdown (Figure 38(a)), care must
be taken to ensure that no significant leakage current exists
on the shutdown circuitry. This could impact the output
voltage regulation. If the ZCD pin is used for shutdown
(Figure 38(b)), then any parasitic capacitance created by
the shutdown circuitry will add to the delay in detecting the
zero inductor current event.
Figure 38. Shutting Down the PFC Stage by Pulling FB to GND (A) or Pulling ZCD to GND (B)
1
4
3
2
8
5
6
7
FB
Ctrl
Ct
Cs
GND
ZCD
DRV
NCP1606
Shutdown
Shutdown
R
ZCD
R
OUT2
R
OUT1
V
OUT
C
comp
V
CC
1
4
3
2
8
5
6
7
FB
Ctrl
Ct
Cs
GND
ZCD
DRV
NCP1606
V
CC
Figure 38(a) Figure 38(b)
L
BOOST
To activate the shutdown feature on ZCD, the internal
clamp must first be overcome. This clamp will draw a
maximum of I
CL(NEG)
(5.0 mA maximum) before releasing
and allowing the ZCD pin voltage to drop low enough to
shutdown the part (Figure 39). After shutdown, the
comparator includes approximately 90 mV of hysteresis to
ensure noise free operation. A small current source (70 mA
typ) is also activated to pull the unit out of the shutdown
condition when the external pull down is released.
Figure 39. Shutdown Comparator and Current Draw to Overcome Negative Clamp
Shutdown
5 mA
~1 V
V
SDL
V
SDH
I
ZCD
V
CL(NEG)
~70 mA

NCP1606BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC PWR FCTR CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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