HMC903LP3E Data Sheet
Rev. H | Page 10 of 13
APPLICATIONS INFORMATION
Figure 22 shows the basic connections for operating the
HMC903LP3E. Both the RFIN and RFOUT ports have on-chip
dc block capacitors that eliminate the need for external ac
coupling capacitors.
The HMC903LP3E has V
GG1
and V
GG2
optional gate bias pins.
When these pins are left open, the amplifier runs in self biased
operation with a typical I
DQ
= 80 mA, when V
DD1
/V
DD2
= 3.5 V.
When using the V
GG1
and V
GG2
gate bias pins, follow the
recommended bias sequencing so that the amplifier is not
damaged.
RECOMMENDED BIAS SEQUENCE DURING
POWER UP
The recommended bias sequence to power up the
HMC903LP3E is as follows:
1. Connect to GND.
2. Set V
GG1
and V
GG2
to −2 V.
3. Set V
DD1
and V
DD2
to 3.5 V.
4. Increase V
GG1
and V
GG2
to achieve a typical I
DQ
= 80 mA.
5. Apply the RF signal.
RECOMMENDED BIAS SEQUENCE DURING POWER
DOWN
The recommended bias sequence to power down the
HMC903LP3E is as follows:
1. Turn off t he RF signal.
2. Decrease V
GG1
and V
GG2
to −2 V to achieve a typical I
DQ
=
0 mA.
3. Decrease V
DD1
and V
DD2
to 0 V.
4. Increase V
GG1
and V
GG2
to 0 V.
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 23), with
the evaluation board (see Figure 22) and biased per the conditions
in this section. The V
DD1
and V
DD2
pins are connected together;
similarly, the V
GG1
and V
GG2
pins are also connected together. The
bias conditions shown in this section are the operating points
recommended to optimize the overall performance. Operation
using other bias conditions may provide performance that differs
from what is shown in this data sheet.
Decreasing the V
DD1
and V
DD2
levels has negligible effect on the
gain and noise figure performance; however, they reduce the
P1dB. This behavior is shown in Figure 8 to Figure 20. For
applications where the P1dB requirement is not stringent, the
HMC903LP3E can be down biased to reduce power
consumption.
